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* ice40: Fix path delay definitionsStefan Riesenberger2023-03-101-14/+14
| | | | | | Parallel connections do not allow matching different bit widths. A full connection has to be used instead. Allows iverilog to parse the simulation library with hardware path delays enabled.
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-2/+2
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* Order ports with default assignments firstSean Anderson2022-08-091-10/+38
| | | | | | | | | | | | | | Although the current style is allowed by the standard, Icarus verilog doesn't parse default assignments using an implicit net type: techlibs/ice40/cells_sim.v:305: syntax error techlibs/ice40/cells_sim.v:1: Errors in port declarations. Fix this by making sure that ports with default assignments first on their line. Fixes: 46d3f03d2 ("Add default assignments to other SB_* simulation models") Signed-off-by: Sean Anderson <seanga2@gmail.com>
* Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}.Marcelina Kościelnicka2022-06-021-3/+19
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* ice40: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-188-458/+293
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* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
| | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
* ice40: Fix typo in SB_CARRY specify for LP/UltraPlusSylvain Munaut2021-08-171-2/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-1/+1
| | | | Fixes #2061.
* ice40: Fix LUT input indices in opt_lut -dlogic (again).Marcelina Kościelnicka2021-07-101-1/+1
| | | | Fixes #2061.
* Fix icestorm linksClaire Xenia Wolf2021-06-092-516/+516
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-084-4/+4
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* Add default assignments to other SB_* simulation modelsClaire Xenia Wolf2021-04-201-24/+44
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add default assignments to SB_LUT4Claire Xenia Wolf2021-04-201-1/+17
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Blackbox all whiteboxes after synthesisgatecat2021-03-171-0/+1
| | | | | | | This prevents issues like processes in whiteboxes triggering an error in the JSON backend. Signed-off-by: gatecat <gatecat@ds0.me>
* verilog: significant block scoping improvementsZachary Snow2021-01-311-33/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-3/+1
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* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-304-142/+6
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* ice40: Use dfflegalize.Marcelina Kościelnicka2020-07-054-208/+24
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* Update dff2dffe, dff2dffs, zinit to new FF types.Marcelina Kościelnicka2020-06-232-9/+9
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* Use C++11 final/override keywords.whitequark2020-06-185-13/+13
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* Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTHXark2020-06-141-7/+7
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* Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-192-0/+9
| | | | Fixes #2058.
* xilinx/ice40/ecp5: zinit requires selected wires, so select them allEddie Hung2020-05-141-1/+1
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* xilinx/ecp5/ice40: add (* abc9_flop *) to bypass-able cellsEddie Hung2020-05-141-0/+153
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* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-1/+1
| | | | | Eliminate need for abc9_{,un}map.v in xilinx -prep_dff_{hier,unmap} -> -prep_hier
* synth_*: no need to explicitly read +/abc9_model.vEddie Hung2020-05-141-1/+1
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* ice40: synth_ice40 cleanupEddie Hung2020-05-141-13/+3
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* ice40: add synth_ice40 -dff option, support with -abc9Eddie Hung2020-05-142-8/+41
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* ice40: split out cells_map.v into ff_map.vEddie Hung2020-05-143-31/+29
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* ice40: fix ICESTORM_LC process sensitivityEddie Hung2020-05-121-1/+1
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* ice40: fix whitespaceEddie Hung2020-05-121-15/+14
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* synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpadEddie Hung2020-05-041-8/+16
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-1/+0
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-102-1/+63
|\ | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-1/+3
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| * ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+1
| | | | | | | | LSE/Synplify use case insensitive matching.
| * ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-061-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
* | kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-024-75/+75
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* | kernel: use more ID::*Eddie Hung2020-04-023-17/+17
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* | Fix indentation in `techlibs/ice40/synth_ice40.cc`.Alberto Gonzalez2020-04-011-4/+4
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* | Merge pull request #1794 from YosysHQ/dave/mince-abc9-fixDavid Shah2020-03-211-0/+1
|\ \ | | | | | | ice40: Map unmapped 'mince' DFFs to gate level
| * | ice40: Map unmapped 'mince' DFFs to gate levelDavid Shah2020-03-201-0/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | ice40: Fix typos in SPRAM ABC9 timing specsSylvain Munaut2020-03-201-2/+2
|/ / | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: Fix SPRAM model to keep data stable if chipselect is lowSylvain Munaut2020-03-141-5/+8
| | | | | | | | | | | | | | | | According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | ice40: fix specify for ICE40_{LP,U}Eddie Hung2020-03-051-4/+4
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* | ice40: fix implicit signal in specify, also clamp negative times to 0Eddie Hung2020-03-041-22/+22
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* | Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabcN. Engelhardt2020-03-031-4/+22
|\ \ | | | | | | Add -flowmap option to `synth{,_ice40}`
| * | Add -flowmap to synth and synth_ice40Dan Ravensloft2020-02-281-4/+22
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* | ice40: add delays to SB_CARRYEddie Hung2020-02-271-0/+30
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* | More +/ice40/cells_sim.v fixesEddie Hung2020-02-271-27/+27
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