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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 10:48:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-04 10:48:44 -0700 |
| commit | 9fef1df3c1431cff2e097a10a502f77f04986a60 (patch) | |
| tree | f8b4c2b66db08476f3d623f7e1a1d6f57ec7b058 /techlibs/ice40 | |
| parent | 4e11782cde412ce80ee8125dd9d55fe21945737f (diff) | |
| download | yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.tar.gz yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.tar.bz2 yosys-9fef1df3c1431cff2e097a10a502f77f04986a60.zip | |
Panic over. Model was elsewhere. Re-arrange for consistency
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/Makefile.inc | 1 | ||||
| -rw-r--r-- | techlibs/ice40/abc_model.v | 2 | ||||
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 28 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 3 |
4 files changed, 3 insertions, 31 deletions
diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 92a9956ea..0fbca9034 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -28,6 +28,7 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/dsp_map.v)) +$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_model.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box)) diff --git a/techlibs/ice40/abc_model.v b/techlibs/ice40/abc_model.v index 8e1827043..fe31b8811 100644 --- a/techlibs/ice40/abc_model.v +++ b/techlibs/ice40/abc_model.v @@ -25,5 +25,3 @@ module \$__ICE40_CARRY_WRAPPER ( .O(O) ); endmodule - - diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 8e5e0358e..16a893226 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -145,34 +145,6 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, lib_whitebox *) -module \$__ICE40_CARRY_WRAPPER ( - (* abc_carry *) - output CO, - output O, - input A, B, - (* abc_carry *) - input CI, - input I0, I3 -); - parameter LUT = 0; - SB_CARRY carry ( - .I0(A), - .I1(B), - .CI(CI), - .CO(CO) - ); - SB_LUT4 #( - .LUT_INIT(LUT) - ) adder ( - .I0(I0), - .I1(A), - .I2(B), - .I3(I3), - .O(O) - ); -endmodule - // Max delay from: https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_hx1k.txt#L90 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_lp1k.txt#L90 // https://github.com/cliffordwolf/icestorm/blob/95949315364f8d9b0c693386aefadf44b28e2cf6/icefuzz/timings_up5k.txt#L102 diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 841f10244..2e4684c19 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass define = "-D ICE40_U"; else define = "-D ICE40_HX"; - run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v"); + run("read_verilog " + define + " -lib +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } @@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass } if (!noabc) { if (abc == "abc9") { + run("read_verilog -icells -lib +/ice40/abc_model.v"); int wire_delay; if (device_opt == "lp") wire_delay = 400; |