| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Squelch trailing whitespace, including meta-whitespace | Larry Doolittle | 2018-03-11 | 1 | -3/+3 |
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| * | Fix port names in SB_IO_OD | Graham Edgecombe | 2017-12-10 | 1 | -18/+18 |
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| * | Remove trailing comma from SB_IO_OD port list | Graham Edgecombe | 2017-12-10 | 1 | -1/+1 |
| | | | | | This isn't compatible with Icarus Verilog. | ||||
| * | Fix spelling in -vpr help for synth_ice40 | Tim Ansell | 2017-12-08 | 1 | -1/+1 |
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| * | Add remaining UltraPlus cells to ice40 techlib | David Shah | 2017-11-28 | 1 | -0/+263 |
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| * | Remove unnecessary keep attributes | David Shah | 2017-11-18 | 1 | -5/+5 |
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| * | Merge branch 'master' into up5k | David Shah | 2017-11-17 | 2 | -5/+29 |
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| | * | Add "synth_ice40 -vpr" | Clifford Wolf | 2017-11-16 | 2 | -5/+29 |
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| * | | Add some UltraPlus cells to ice40 techlib | David Shah | 2017-11-16 | 1 | -0/+103 |
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| * | Fix synth_ice40 doc regarding -top default | Clifford Wolf | 2017-09-29 | 1 | -1/+1 |
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| * | iCE40 flow is not experimental anymore | Clifford Wolf | 2016-11-01 | 1 | -1/+1 |
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| * | Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations | Clifford Wolf | 2016-07-08 | 2 | -13/+24 |
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| * | Improved ice40_ffinit error reporting | Clifford Wolf | 2016-06-30 | 1 | -1/+5 |
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| * | Added "deminout" | Clifford Wolf | 2016-06-19 | 1 | -0/+1 |
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| * | Added synth_ice40 support for latches via logic loops | Clifford Wolf | 2016-05-06 | 3 | -0/+13 |
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| * | Fixed ice40_opt lut unmapping, added "ice40_opt -unlut" | Clifford Wolf | 2016-05-06 | 1 | -3/+15 |
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| * | Converted synth_greenpak4 to ScriptPass | Clifford Wolf | 2016-04-23 | 1 | -3/+2 |
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| * | Added "yosys -D" feature | Clifford Wolf | 2016-04-21 | 4 | -7/+7 |
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| * | Added ScriptPass helper class for script-like passes | Clifford Wolf | 2016-03-31 | 1 | -126/+79 |
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| * | Renamed opt_share to opt_merge | Clifford Wolf | 2016-03-31 | 1 | -2/+2 |
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| * | Renamed opt_const to opt_expr | Clifford Wolf | 2016-03-31 | 2 | -6/+6 |
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| * | Work around DDR dout sim glitches in ice40 SB_IO sim model | Clifford Wolf | 2016-02-07 | 1 | -1/+7 |
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| * | Added dffsr2dff | Clifford Wolf | 2016-02-02 | 1 | -0/+2 |
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| * | Re-run ice40_opt in "synth_ice40 -abc2" | Clifford Wolf | 2015-12-22 | 1 | -1/+4 |
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| * | Improvements in ice40_opt | Clifford Wolf | 2015-12-22 | 1 | -5/+16 |
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| * | Bugfix in ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -2/+2 |
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| * | Improved ice40_ffinit | Clifford Wolf | 2015-12-22 | 1 | -1/+22 |
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| * | Added "synth_ice40 -abc2" | Clifford Wolf | 2015-12-08 | 1 | -0/+11 |
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| * | Merge pull request #108 from cseed/master | Clifford Wolf | 2015-12-07 | 1 | -1/+3 |
| |\ | | | | | Added LO to ICESTORM_LC for LUT cascade route. | ||||
| | * | Added LO to ICESTORM_LC for LUT cascade route. | Cotton Seed | 2015-12-06 | 1 | -1/+3 |
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| * | | Added ice40_ffinit pass | Clifford Wolf | 2015-11-26 | 3 | -0/+145 |
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| * | | Fixed WE/RE usage in iCE40 BRAM mapping | Clifford Wolf | 2015-11-24 | 1 | -8/+8 |
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| * | | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling | Clifford Wolf | 2015-11-06 | 1 | -2/+2 |
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| * | | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 2 | -6/+8 |
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| * | | Fixed ice40 handling of negclk RAM40 | Clifford Wolf | 2015-09-10 | 2 | -12/+12 |
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| * | | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 2 | -5/+2 |
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| * | Another bugfix for ice40 and xilinx brams_init make rules | Clifford Wolf | 2015-08-16 | 2 | -4/+4 |
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| * | Fixed Makefile rules for generated share files | Clifford Wolf | 2015-08-16 | 1 | -1/+6 |
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| * | Added tribuf command | Clifford Wolf | 2015-08-16 | 1 | -0/+2 |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -4/+1 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Improved handling of "keep" attributes in hierarchical designs in opt_clean | Clifford Wolf | 2015-08-12 | 1 | -2/+1 |
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| * | Added iCE40 WARMBOOT cell | Marcus Comstedt | 2015-08-06 | 1 | -0/+10 |
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| * | Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) | Clifford Wolf | 2015-07-27 | 1 | -1/+0 |
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| * | iCE40 DFF sim models: init Q regs to 0 | Clifford Wolf | 2015-07-20 | 1 | -20/+43 |
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| * | Avoid tristate warning for blackbox ice40/cells_sim.v | Clifford Wolf | 2015-07-18 | 1 | -0/+2 |
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| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 5 | -13/+13 |
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| * | iCE40: set min bram efficiency to 2% | Clifford Wolf | 2015-06-20 | 1 | -2/+2 |
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| * | synth_ice40 now flattens by default | Clifford Wolf | 2015-06-09 | 1 | -4/+8 |
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| * | Added iCE40 PLL cells | Clifford Wolf | 2015-05-31 | 1 | -0/+168 |
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| * | Added output args to synth_ice40 | Clifford Wolf | 2015-05-26 | 1 | -0/+35 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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