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| author | Larry Doolittle <ldoolitt@recycle.lbl.gov> | 2018-03-10 09:59:06 -0800 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-03-11 16:03:41 +0100 |
| commit | efaef82f75d8e477baf958eac39f538e6eed5b03 (patch) | |
| tree | 6153ab94c5cbf400c5c685128e1a741cd661534c /techlibs/ice40 | |
| parent | 82fecc98c01dd3883b7d8268d3f1c7c35512f00d (diff) | |
| download | yosys-efaef82f75d8e477baf958eac39f538e6eed5b03.tar.gz yosys-efaef82f75d8e477baf958eac39f538e6eed5b03.tar.bz2 yosys-efaef82f75d8e477baf958eac39f538e6eed5b03.zip | |
Squelch trailing whitespace, including meta-whitespace
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 3be5ed28e..814895e70 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -912,7 +912,7 @@ module SB_MAC16 ( output CO, output ACCUMCO, output SIGNEXTOUT -); +); parameter NEG_TRIGGER = 1'b0; parameter C_REG = 1'b0; parameter A_REG = 1'b0; @@ -1030,7 +1030,7 @@ endmodule (* blackbox *) module SB_SPI ( input SBCLKI, - input SBRWI, + input SBRWI, input SBSTBI, input SBADRI7, input SBADRI6, @@ -1125,7 +1125,7 @@ module SB_IO_I3C ( input D_OUT_1, output D_IN_0, output D_IN_1, - input PU_ENB, + input PU_ENB, input WEAK_PU_ENB ); parameter [5:0] PIN_TYPE = 6'b000000; |