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| author | Clifford Wolf <clifford@clifford.at> | 2015-12-22 12:18:38 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-12-22 12:18:38 +0100 |
| commit | 3102ffbb83574b3abaebef513bb762d5e951cda0 (patch) | |
| tree | 44171908a49cb462b290f89504732bae4addfab7 /techlibs/ice40 | |
| parent | 8bf452c364b4b5aed128927b9d12a1373c0b7c71 (diff) | |
| download | yosys-3102ffbb83574b3abaebef513bb762d5e951cda0.tar.gz yosys-3102ffbb83574b3abaebef513bb762d5e951cda0.tar.bz2 yosys-3102ffbb83574b3abaebef513bb762d5e951cda0.zip | |
Improvements in ice40_opt
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 6acefaf49..677ac8d77 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -76,13 +76,24 @@ static void run_ice40_opts(Module *module) for (auto cell : sb_lut_cells) { - if (optimized_co.count(sigmap(cell->getPort("\\I0")))) goto remap_lut; - if (optimized_co.count(sigmap(cell->getPort("\\I1")))) goto remap_lut; - if (optimized_co.count(sigmap(cell->getPort("\\I2")))) goto remap_lut; - if (optimized_co.count(sigmap(cell->getPort("\\I3")))) goto remap_lut; - continue; + SigSpec inbits; + + inbits.append(cell->getPort("\\I0")); + inbits.append(cell->getPort("\\I1")); + inbits.append(cell->getPort("\\I2")); + inbits.append(cell->getPort("\\I3")); + sigmap.apply(inbits); + + if (optimized_co.count(inbits[0])) goto remap_lut; + if (optimized_co.count(inbits[1])) goto remap_lut; + if (optimized_co.count(inbits[2])) goto remap_lut; + if (optimized_co.count(inbits[3])) goto remap_lut; + + if (!sigmap(inbits).is_fully_const()) + continue; remap_lut: + module->design->scratchpad_set_bool("opt.did_something", true); log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell)); cell->type ="$lut"; |