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| author | Tim Ansell <mithro@mithis.com> | 2017-12-08 18:44:45 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-12-08 18:44:45 -0800 |
| commit | 3cc31f197cf69b6644928a58bf58028d65e38e60 (patch) | |
| tree | 76201aafcd71f89448f4b839fc73c7302dc14757 /techlibs/ice40 | |
| parent | 8f2638ae2f12a48dcad14f24b0211c16ac724762 (diff) | |
| download | yosys-3cc31f197cf69b6644928a58bf58028d65e38e60.tar.gz yosys-3cc31f197cf69b6644928a58bf58028d65e38e60.tar.bz2 yosys-3cc31f197cf69b6644928a58bf58028d65e38e60.zip | |
Fix spelling in -vpr help for synth_ice40
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 57f96ca1a..0bb0fb139 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -70,7 +70,7 @@ struct SynthIce40Pass : public ScriptPass log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); - log(" (this fueature is experimental and incomplete)\n"); + log(" (this feature is experimental and incomplete)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); |