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| author | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-09-25 12:23:11 +0200 |
| commit | 924d9d6e86a5e9a2294479345daac1c03d78008a (patch) | |
| tree | 04d28a2068b32c44c0aca2b8b815f6fc51cec427 /techlibs/ice40 | |
| parent | ec92c8965960fa814c3663e987bc2a7eb80965e5 (diff) | |
| download | yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.gz yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.tar.bz2 yosys-924d9d6e86a5e9a2294479345daac1c03d78008a.zip | |
Added read-enable to memory model
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/brams.txt | 4 | ||||
| -rw-r--r-- | techlibs/ice40/brams_map.v | 10 |
2 files changed, 8 insertions, 6 deletions
diff --git a/techlibs/ice40/brams.txt b/techlibs/ice40/brams.txt index 05131b227..03d596111 100644 --- a/techlibs/ice40/brams.txt +++ b/techlibs/ice40/brams.txt @@ -5,7 +5,7 @@ bram $__ICE40_RAM4K_M0 groups 2 ports 1 1 wrmode 0 1 - enable 0 16 + enable 1 16 transp 0 0 clocks 2 3 clkpol 2 3 @@ -22,7 +22,7 @@ bram $__ICE40_RAM4K_M123 groups 2 ports 1 1 wrmode 0 1 - enable 0 1 + enable 1 1 transp 0 0 clocks 2 3 clkpol 2 3 diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index f3674b4ed..a82161c99 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -168,7 +168,7 @@ module \$__ICE40_RAM4K ( endmodule -module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter [0:0] CLKPOL2 = 1; parameter [0:0] CLKPOL3 = 1; @@ -179,6 +179,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [7:0] A1ADDR; output [15:0] A1DATA; + input A1EN; input [7:0] B1ADDR; input [15:0] B1DATA; @@ -213,7 +214,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), - .RE(1'b1), + .RE(A1EN), .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), @@ -223,7 +224,7 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); ); endmodule -module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); +module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 9; parameter CFG_DBITS = 8; @@ -242,6 +243,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; + input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; @@ -298,7 +300,7 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN); .RADDR(A1ADDR_11), .RCLK(CLK2), .RCLKE(1'b1), - .RE(1'b1), + .RE(A1EN), .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), |