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| author | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-04-21 23:28:37 +0200 |
| commit | 0bc95f1e049afc35bb5ea30663b0a5725dfbf584 (patch) | |
| tree | 3a8641d3a9bb5794a24145ce368f3db7a3963709 /techlibs/ice40 | |
| parent | 1565d1af69f552b790aa43fd6be194ee59ab76f3 (diff) | |
| download | yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.gz yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.tar.bz2 yosys-0bc95f1e049afc35bb5ea30663b0a5725dfbf584.zip | |
Added "yosys -D" feature
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_ffinit.cc | 2 | ||||
| -rw-r--r-- | techlibs/ice40/ice40_ffssr.cc | 2 | ||||
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 8 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
4 files changed, 7 insertions, 7 deletions
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc index 8c4b9a37d..db2100381 100644 --- a/techlibs/ice40/ice40_ffinit.cc +++ b/techlibs/ice40/ice40_ffinit.cc @@ -37,7 +37,7 @@ struct Ice40FfinitPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing ICE40_FFINIT pass (implement FF init values).\n"); + log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc index 9ebc3c0d7..9a6d69df0 100644 --- a/techlibs/ice40/ice40_ffssr.cc +++ b/techlibs/ice40/ice40_ffssr.cc @@ -35,7 +35,7 @@ struct Ice40FfssrPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); + log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index 5730847ce..8b6a23fb2 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -137,7 +137,7 @@ struct Ice40OptPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { string opt_expr_args = "-mux_undef -undriven"; - log_header("Executing ICE40_OPT pass (performing simple optimizations).\n"); + log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n"); log_push(); size_t argidx; @@ -154,7 +154,7 @@ struct Ice40OptPass : public Pass { { design->scratchpad_unset("opt.did_something"); - log_header("Running ICE40 specific optimizations.\n"); + log_header(design, "Running ICE40 specific optimizations.\n"); for (auto module : design->selected_modules()) run_ice40_opts(module); @@ -166,14 +166,14 @@ struct Ice40OptPass : public Pass { if (design->scratchpad_get_bool("opt.did_something") == false) break; - log_header("Rerunning OPT passes. (Removed registers in this run.)\n"); + log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n"); } design->optimize(); design->sort(); design->check(); - log_header("Finished OPT passes. (There is nothing left to do.)\n"); + log_header(design, "Finished OPT passes. (There is nothing left to do.)\n"); log_pop(); } } Ice40OptPass; diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 2ed7642ae..3dbdde3df 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -149,7 +149,7 @@ struct SynthIce40Pass : public ScriptPass if (!design->full_selection()) log_cmd_error("This comannd only operates on fully selected designs!\n"); - log_header("Executing SYNTH_ICE40 pass.\n"); + log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); run_script(design, run_from, run_to); |