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| author | Clifford Wolf <clifford@clifford.at> | 2015-11-24 10:51:34 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-11-24 10:51:34 +0100 |
| commit | 8ff229a3ead38f89b0dddde9d952c8677d89f980 (patch) | |
| tree | 183c8d1d40e091492fcd7601443a38355dc050a9 /techlibs/ice40 | |
| parent | c86fbae3d11d4d835233996711e4ff1e92ee29d9 (diff) | |
| download | yosys-8ff229a3ead38f89b0dddde9d952c8677d89f980.tar.gz yosys-8ff229a3ead38f89b0dddde9d952c8677d89f980.tar.bz2 yosys-8ff229a3ead38f89b0dddde9d952c8677d89f980.zip | |
Fixed WE/RE usage in iCE40 BRAM mapping
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/brams_map.v | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index a82161c99..19a61d73b 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -213,14 +213,14 @@ module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1E .RDATA(A1DATA), .RADDR(A1ADDR_11), .RCLK(CLK2), - .RCLKE(1'b1), - .RE(A1EN), + .RCLKE(A1EN), + .RE(1'b1), .WDATA(B1DATA), .WADDR(B1ADDR_11), .MASK(~B1EN), .WCLK(CLK3), - .WCLKE(1'b1), - .WE(|B1EN) + .WCLKE(|B1EN), + .WE(1'b1) ); endmodule @@ -299,13 +299,13 @@ module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B .RDATA(A1DATA_16), .RADDR(A1ADDR_11), .RCLK(CLK2), - .RCLKE(1'b1), - .RE(A1EN), + .RCLKE(A1EN), + .RE(1'b1), .WDATA(B1DATA_16), .WADDR(B1ADDR_11), .WCLK(CLK3), - .WCLKE(1'b1), - .WE(|B1EN) + .WCLKE(|B1EN), + .WE(1'b1) ); endmodule |