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* Squelch trailing whitespace, including meta-whitespaceLarry Doolittle2018-03-111-3/+3
* Fix port names in SB_IO_ODGraham Edgecombe2017-12-101-18/+18
* Remove trailing comma from SB_IO_OD port listGraham Edgecombe2017-12-101-1/+1
* Fix spelling in -vpr help for synth_ice40Tim Ansell2017-12-081-1/+1
* Add remaining UltraPlus cells to ice40 techlibDavid Shah2017-11-281-0/+263
* Remove unnecessary keep attributesDavid Shah2017-11-181-5/+5
* Merge branch 'master' into up5kDavid Shah2017-11-172-5/+29
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| * Add "synth_ice40 -vpr"Clifford Wolf2017-11-162-5/+29
* | Add some UltraPlus cells to ice40 techlibDavid Shah2017-11-161-0/+103
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* Fix synth_ice40 doc regarding -top defaultClifford Wolf2017-09-291-1/+1
* iCE40 flow is not experimental anymoreClifford Wolf2016-11-011-1/+1
* Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiationsClifford Wolf2016-07-082-13/+24
* Improved ice40_ffinit error reportingClifford Wolf2016-06-301-1/+5
* Added "deminout"Clifford Wolf2016-06-191-0/+1
* Added synth_ice40 support for latches via logic loopsClifford Wolf2016-05-063-0/+13
* Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"Clifford Wolf2016-05-061-3/+15
* Converted synth_greenpak4 to ScriptPassClifford Wolf2016-04-231-3/+2
* Added "yosys -D" featureClifford Wolf2016-04-214-7/+7
* Added ScriptPass helper class for script-like passesClifford Wolf2016-03-311-126/+79
* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-2/+2
* Renamed opt_const to opt_exprClifford Wolf2016-03-312-6/+6
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-071-1/+7
* Added dffsr2dffClifford Wolf2016-02-021-0/+2
* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-221-1/+4
* Improvements in ice40_optClifford Wolf2015-12-221-5/+16
* Bugfix in ice40_ffinitClifford Wolf2015-12-221-2/+2
* Improved ice40_ffinitClifford Wolf2015-12-221-1/+22
* Added "synth_ice40 -abc2"Clifford Wolf2015-12-081-0/+11
* Merge pull request #108 from cseed/masterClifford Wolf2015-12-071-1/+3
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| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-061-1/+3
* | Added ice40_ffinit passClifford Wolf2015-11-263-0/+145
* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-241-8/+8
* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-061-2/+2
* | Added read-enable to memory modelClifford Wolf2015-09-252-6/+8
* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-102-12/+12
* | Switched to Python 3Clifford Wolf2015-08-222-5/+2
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* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-162-4/+4
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-161-1/+6
* Added tribuf commandClifford Wolf2015-08-161-0/+2
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-121-4/+1
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-121-2/+1
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-061-0/+10
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-271-1/+0
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-201-20/+43
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-181-0/+2
* Fixed trailing whitespacesClifford Wolf2015-07-025-13/+13
* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-201-2/+2
* synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
* Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
* Added output args to synth_ice40Clifford Wolf2015-05-261-0/+35
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