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* Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
* Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-281-7/+33
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| * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-251-0/+17
| * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
* | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
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* ecp5: Adding some blackbox cellsDavid Shah2018-11-071-1/+1
* ecp5: Sim model fixesDavid Shah2018-10-191-3/+5
* ecp5: First BRAM type maps successfullyDavid Shah2018-10-101-0/+2
* ecp5: Script for BRAM IO connectionsDavid Shah2018-10-101-64/+64
* ecp5: Adding BRAM initialisation and configDavid Shah2018-10-091-0/+4
* ecp5: Add blackbox for DP16KDDavid Shah2018-10-051-0/+93
* ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
* ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
* ecp5: ECP5 synthesis fixesDavid Shah2018-07-161-13/+26
* ecp5: Cells and mappings fixesDavid Shah2018-07-131-2/+2
* ecp5: Adding DFF mapsDavid Shah2018-07-131-1/+1
* ecp5: Adding DRAM mapDavid Shah2018-07-131-1/+36
* ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-131-0/+387
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