| Commit message (Expand) | Author | Age | Files | Lines |
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| * | DSP_MINWIDTH -> DSP_{A,B,Y}_MINWIDTH | Eddie Hung | 2019-08-01 | 1 | -4/+11 |
| * | Revert "Do not do sign extension in techmap; let packer do it" | Eddie Hung | 2019-08-01 | 1 | -5/+14 |
| * | Fix B_WIDTH > DSP_B_MAXWIDTH case | Eddie Hung | 2019-08-01 | 1 | -32/+14 |
| * | Do not compute sign bit if result is zero | Eddie Hung | 2019-07-31 | 1 | -1/+2 |
| * | For signed multipliers, compute sign bit separately... | Eddie Hung | 2019-07-31 | 1 | -23/+42 |
| * | Fix spacing | Eddie Hung | 2019-07-26 | 1 | -3/+3 |
| * | Add copyright header, comment on cascade | Eddie Hung | 2019-07-24 | 1 | -4/+34 |
| * | Typo for Y_WIDTH | Eddie Hung | 2019-07-23 | 1 | -1/+1 |
| * | Use minimum sized width wires | Eddie Hung | 2019-07-22 | 1 | -7/+13 |
| * | Indirection via $__soft_mul | Eddie Hung | 2019-07-19 | 1 | -9/+9 |
| * | Do not do sign extension in techmap; let packer do it | Eddie Hung | 2019-07-19 | 1 | -14/+5 |
| * | Do not $mul -> $__mul if A and B are less than maxwidth | Eddie Hung | 2019-07-19 | 1 | -1/+3 |
| * | Add a DSP_MINWIDTH macro, and soft-logic for {A_WIDTH,B_WIDTH} <= 1 too | Eddie Hung | 2019-07-19 | 1 | -28/+68 |
| * | Merge branch 'xc7dsp' into ice40dsp | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
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| | * | Fix typo in B | Eddie Hung | 2019-07-19 | 1 | -1/+1 |
| | * | Merge remote-tracking branch 'origin/master' into xc7dsp | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
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| * | | | Use sign_headroom instead | Eddie Hung | 2019-07-19 | 1 | -4/+4 |
| * | | | Do not define `DSP_SIGNEDONLY macro if no exists | Eddie Hung | 2019-07-18 | 1 | -4/+3 |
| * | | | Merge remote-tracking branch 'origin/master' into ice40dsp | Eddie Hung | 2019-07-18 | 1 | -1/+1 |
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| | * | | gen_lut to return correctly sized LUT mask | Eddie Hung | 2019-07-16 | 1 | -1/+1 |
| | * | | Revert "Add "synth -keepdc" option" | Eddie Hung | 2019-07-09 | 1 | -13/+2 |
| | * | | Add synth -keepdc option | Eddie Hung | 2019-07-08 | 1 | -2/+13 |
| * | | | mul2dsp to create cells that can be interchanged with $mul | Eddie Hung | 2019-07-18 | 1 | -1/+7 |
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| * | | Make consistent | Eddie Hung | 2019-07-18 | 1 | -1/+2 |
| * | | Fix signed multiplier decomposition | Eddie Hung | 2019-07-18 | 1 | -29/+36 |
| * | | Working for unsigned | Eddie Hung | 2019-07-18 | 1 | -52/+28 |
| * | | Cleanup | Eddie Hung | 2019-07-18 | 1 | -70/+58 |
| * | | mul2dsp: Lower partial products always have unsigned inputs | David Shah | 2019-07-18 | 1 | -31/+41 |
| * | | Fix mul2dsp signedness | Eddie Hung | 2019-07-17 | 1 | -42/+38 |
| * | | A_SIGNED == B_SIGNED so flip both | Eddie Hung | 2019-07-17 | 1 | -21/+12 |
| * | | Add DSP_{A,B}_SIGNEDONLY macro | Eddie Hung | 2019-07-16 | 1 | -11/+40 |
| * | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp | Eddie Hung | 2019-07-16 | 1 | -22/+26 |
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| | * | | mul2dsp: Fix edge case where Y_WIDTH is less than B_WIDTH+`DSP_A_MAXWIDTH | David Shah | 2019-07-16 | 1 | -18/+22 |
| | * | | mul2dsp: Fix indentation | David Shah | 2019-07-16 | 1 | -7/+7 |
| * | | | Do not swap if equals | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
| * | | | OUT port to Y in generic DSP | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
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| * | | Only swap if B_WIDTH > A_WIDTH | Eddie Hung | 2019-07-15 | 1 | -1/+1 |
| * | | Tidy up | Eddie Hung | 2019-07-15 | 1 | -39/+26 |
| * | | mul2dsp: Fix typo | David Shah | 2019-07-08 | 1 | -1/+1 |
| * | | Add mul2dsp multiplier splitting rule and ECP5 mapping | David Shah | 2019-07-08 | 2 | -0/+238 |
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| * | Make doc consistent | Eddie Hung | 2019-06-14 | 1 | -1/+4 |
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 3 | -2/+182 |
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| | * | Add "wreduce -keepdc", fixes #1016 | Clifford Wolf | 2019-05-20 | 1 | -2/+4 |
| | * | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 1 | -0/+2 |
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| | | * | Run "peepopt" in generic "synth" pass and "synth_ice40" | Clifford Wolf | 2019-04-30 | 1 | -0/+2 |
| | * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | * | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -3/+4 |
| | * | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 1 | -0/+28 |
| | * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -70/+70 |
| | * | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 |
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