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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 11:24:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-15 11:24:11 -0700 |
| commit | 91fcf034bceecd50f1aaf96c3cdc270250ab9597 (patch) | |
| tree | 4566cc653e4efe253a1e89dc0e84eb3a9c9daccd /techlibs/common | |
| parent | 1793e6018a37af674a356769779674e095fae261 (diff) | |
| download | yosys-91fcf034bceecd50f1aaf96c3cdc270250ab9597.tar.gz yosys-91fcf034bceecd50f1aaf96c3cdc270250ab9597.tar.bz2 yosys-91fcf034bceecd50f1aaf96c3cdc270250ab9597.zip | |
Only swap if B_WIDTH > A_WIDTH
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/mul2dsp.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v index d2e68987b..0eec4cc82 100644 --- a/techlibs/common/mul2dsp.v +++ b/techlibs/common/mul2dsp.v @@ -33,7 +33,7 @@ module \$mul (A, B, Y); output [Y_WIDTH-1:0] Y;
generate
- if (A_WIDTH < B_WIDTH)
+ if (B_WIDTH < A_WIDTH)
\$__mul_gen #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
|