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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:57:10 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 22:57:10 +0200 |
| commit | 64925b4e8f7890f5447d9655b2c69dd59a93f7cd (patch) | |
| tree | 393ed31a9228a475077864ef5419412d1910212b /techlibs/common | |
| parent | 4575e4ad86494e99dd05200f7242dfa632053c78 (diff) | |
| download | yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.tar.gz yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.tar.bz2 yosys-64925b4e8f7890f5447d9655b2c69dd59a93f7cd.zip | |
Improve $specrule interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/simlib.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 965242cdc..a424d3089 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1419,9 +1419,9 @@ endmodule module \$specrule (EN_SRC, EN_DST, SRC, DST); -parameter SKEW = 0; -parameter HOLD = 0; +parameter TYPE = ""; parameter T_LIMIT = 0; +parameter T_LIMIT2 = 0; parameter SRC_WIDTH = 1; parameter DST_WIDTH = 1; |