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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:32:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:32:46 -0700 |
| commit | 627a62a797ef9e676ba9d89f53f927d0c2463585 (patch) | |
| tree | 5bee8befafcb57b64ae08f0ae4db17cbaf18009d /techlibs/common | |
| parent | 1656c44373dbf7375c068d5626e38a76b5a83c4d (diff) | |
| download | yosys-627a62a797ef9e676ba9d89f53f927d0c2463585.tar.gz yosys-627a62a797ef9e676ba9d89f53f927d0c2463585.tar.bz2 yosys-627a62a797ef9e676ba9d89f53f927d0c2463585.zip | |
Make doc consistent
Diffstat (limited to 'techlibs/common')
| -rw-r--r-- | techlibs/common/synth.cc | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index ee2e86de9..555de9fba 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -76,7 +76,7 @@ struct SynthPass : public ScriptPass log(" synonymous to the end of the command list.\n"); log("\n"); log(" -abc9\n"); - log(" use abc9 instead of abc\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -174,6 +174,9 @@ struct SynthPass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); + if (abc == "abc9" && !lut) + log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)"); + log_header(design, "Executing SYNTH pass.\n"); log_push(); |