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authorClifford Wolf <clifford@clifford.at>2019-04-23 15:46:40 +0200
committerClifford Wolf <clifford@clifford.at>2019-04-23 21:36:59 +0200
commit71c38d9de527e1a8b55ba295df459fbcf2a0fe47 (patch)
treea51313b07ad0f5029792760cf7a12789a5d97a18 /techlibs/common
parent634482380cfe5d6a1c801af0ce04e8048c5c9baf (diff)
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Add $specrule cells for $setup/$hold/$skew specify rules
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs/common')
-rw-r--r--techlibs/common/simlib.v28
1 files changed, 28 insertions, 0 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index f9e45df67..facecd9a4 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1417,6 +1417,34 @@ endmodule
// --------------------------------------------------------
+module \$specrule (EN_SRC, EN_DST, SRC, DST);
+
+parameter SRC_WIDTH = 1;
+parameter DST_WIDTH = 1;
+
+parameter SRC_PEN = 0;
+parameter SRC_POL = 0;
+
+parameter DST_PEN = 0;
+parameter DST_POL = 0;
+
+parameter LIMIT_GT = 0;
+parameter T_LIMIT = 0;
+
+input EN_SRC, EN_DST;
+input [SRC_WIDTH-1:0] SRC;
+input [DST_WIDTH-1:0] DST;
+
+`ifdef SIMLIB_SPECIFY
+specify
+ // TBD
+endspecify
+`endif
+
+endmodule
+
+// --------------------------------------------------------
+
module \$assert (A, EN);
input A, EN;