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* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-041-9/+4
* Removed $bu0 cell typeClifford Wolf2014-09-043-10/+7
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-013-0/+1342
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-011-1/+1
* Added design->scratchpadClifford Wolf2014-08-308-64/+19
* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-241-0/+35
* Added some additional log messages to opt_constClifford Wolf2014-08-241-1/+10
* Renamed toposort.h to utils.hClifford Wolf2014-08-171-1/+1
* Added "opt -fast"Clifford Wolf2014-08-161-19/+45
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-6/+6
* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-151-2/+2
* RIP $safe_pmuxClifford Wolf2014-08-143-3/+2
* Fixed a performance bug in opt_reduceClifford Wolf2014-08-021-2/+6
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-024-29/+30
* Replaced sha1 implementationClifford Wolf2014-08-012-7/+1
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-315-170/+170
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-7/+9
* Using log_assert() instead of assert()Clifford Wolf2014-07-285-7/+2
* Added SigPool::check(bit)Clifford Wolf2014-07-271-2/+2
* Fixed bug in opt_cleanClifford Wolf2014-07-271-1/+1
* Improved performance of opt_const on large modulesClifford Wolf2014-07-271-29/+54
* Fixed a bug in opt_clean and some RTLIL API usage cleanupsClifford Wolf2014-07-272-13/+14
* Using new obj iterator API in a few placesClifford Wolf2014-07-271-12/+11
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-276-7/+7
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-276-18/+18
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-275-9/+9
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-6/+10
* More RTLIL::Cell API usage cleanupsClifford Wolf2014-07-261-1/+1
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-2/+2
* Manual fixes for new cell connections APIClifford Wolf2014-07-264-24/+32
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-266-195/+195
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-266-195/+195
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-256-22/+9
* Fixed memory corruption in "opt_reduce" passClifford Wolf2014-07-251-5/+7
* Replaced more old SigChunk programming patternsClifford Wolf2014-07-241-9/+4
* Added cover() calls to opt_constClifford Wolf2014-07-241-9/+45
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-232-4/+0
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-234-40/+39
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3Clifford Wolf2014-07-231-1/+1
* Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3Clifford Wolf2014-07-231-1/+1
* SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...Clifford Wolf2014-07-221-7/+2
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-226-89/+89
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-226-89/+89
* Added "opt_const -keepdc"Clifford Wolf2014-07-212-15/+168
* Added mul to mux conversion to "opt_const -fine"Clifford Wolf2014-07-211-0/+55
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-213-15/+144
* Added opt_const support for simple identitiesClifford Wolf2014-07-211-0/+69
* Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN portClifford Wolf2014-07-181-0/+15
* Improved opt_reduce handling of mem wr_en mux bitsClifford Wolf2014-07-171-5/+18
* improved opt_reduce for $mem/$memwr WR_EN multiplexersClifford Wolf2014-07-161-0/+80