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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 15:38:02 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 15:38:02 +0200 |
| commit | 0c86d6106c3ff4cd7628b1206281eb6080f8bf51 (patch) | |
| tree | c5f0b406e7b77434b97fb704c90377892bb1b059 /passes/opt | |
| parent | ddd31a0b66259a458f7bfb3475f53c30aa859bc8 (diff) | |
| download | yosys-0c86d6106c3ff4cd7628b1206281eb6080f8bf51.tar.gz yosys-0c86d6106c3ff4cd7628b1206281eb6080f8bf51.tar.bz2 yosys-0c86d6106c3ff4cd7628b1206281eb6080f8bf51.zip | |
Added SigPool::check(bit)
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 76a905b2c..6c20bddbb 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -251,10 +251,10 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (int i = 0; i < SIZE(sig); i++) { if (sig[i].wire == NULL) continue; - if (!used_signals_nodrivers.check_any(sig[i])) { + if (!used_signals_nodrivers.check(sig[i])) { if (!unused_bits.empty()) unused_bits += " "; - unused_bits += stringf("%zd", i); + unused_bits += stringf("%d", i); } } if (unused_bits.empty() || wire->port_id != 0) |