Manual fixes for new cell connections API

4 files changed, 32 insertions, 24 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index fa5d8f189..e279c0209 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -189,13 +189,13 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		}
 	}
 
-	module->connections().clear();
+	module->connections_.clear();
 
 	SigPool used_signals;
 	SigPool used_signals_nodrivers;
 	for (auto &it : module->cells) {
 		RTLIL::Cell *cell = it.second;
-		for (auto &it2 : cell->connections()) {
+		for (auto &it2 : cell->connections_) {
 			assign_map.apply(it2.second);
 			used_signals.add(it2.second);
 			if (!ct.cell_output(cell->type, it2.first))
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 7f420ec34..e52882316 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -73,7 +73,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
 
 static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)
 {
-	RTLIL::SigSpec Y = cell->connections()[out_port];
+	RTLIL::SigSpec Y = cell->get(out_port);
 	out_val.extend_u0(Y.size(), false);
 
 	log("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
@@ -240,7 +240,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover("opt.opt_const.fine.$reduce_and");
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->get("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -267,7 +267,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
-					cell->get("\\A") = sig_a = new_a;
+					cell->set("\\A", sig_a = new_a);
 					cell->parameters.at("\\A_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -294,7 +294,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
-					cell->get("\\B") = sig_b = new_b;
+					cell->set("\\B", sig_b = new_b);
 					cell->parameters.at("\\B_WIDTH") = 1;
 					OPT_DID_SOMETHING = true;
 					did_something = true;
@@ -441,8 +441,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cover("opt.opt_const.mux_to_inv");
 				cell->type = "$_INV_";
 				cell->set("\\A", input.extract(0, 1));
-				cell->connections().erase("\\B");
-				cell->connections().erase("\\S");
+				cell->unset("\\B");
+				cell->unset("\\S");
 				goto next_cell;
 			}
 			if (input.match("11 ")) ACTION_DO_Y(1);
@@ -510,7 +510,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 			if (a.is_fully_const()) {
 				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
-				std::swap(cell->get("\\A"), cell->get("\\B"));
+				RTLIL::SigSpec tmp = cell->get("\\A");
+				cell->set("\\A", cell->get("\\B"));
+				cell->set("\\B", tmp);
 			}
 
 			if (b.is_fully_const()) {
@@ -522,7 +524,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
-					cell->connections().erase("\\B");
+					cell->unset("\\B");
 				}
 				goto next_cell;
 			}
@@ -585,13 +587,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
 
 				if (!identity_wrt_a) {
-					cell->get("\\A") = cell->get("\\B");
+					cell->set("\\A", cell->get("\\B"));
 					cell->parameters.at("\\A_WIDTH") = cell->parameters.at("\\B_WIDTH");
 					cell->parameters.at("\\A_SIGNED") = cell->parameters.at("\\B_SIGNED");
 				}
 
 				cell->type = identity_bu0 ? "$bu0" : "$pos";
-				cell->connections().erase("\\B");
+				cell->unset("\\B");
 				cell->parameters.erase("\\B_WIDTH");
 				cell->parameters.erase("\\B_SIGNED");
 				cell->check();
@@ -613,8 +615,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				cell->get("\\A") == RTLIL::SigSpec(1, 1) && cell->get("\\B") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
 			cell->set("\\A", cell->get("\\S"));
-			cell->connections().erase("\\B");
-			cell->connections().erase("\\S");
+			cell->unset("\\B");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\Y_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -631,7 +633,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\A") == RTLIL::SigSpec(0, 1)) {
 			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
 			cell->set("\\A", cell->get("\\S"));
-			cell->connections().erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -650,7 +652,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->get("\\B") == RTLIL::SigSpec(1, 1)) {
 			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
 			cell->set("\\B", cell->get("\\S"));
-			cell->connections().erase("\\S");
+			cell->unset("\\S");
 			if (cell->type == "$mux") {
 				cell->parameters["\\A_WIDTH"] = cell->parameters["\\WIDTH"];
 				cell->parameters["\\B_WIDTH"] = cell->parameters["\\WIDTH"];
@@ -701,9 +703,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 			if (cell->get("\\S").size() != new_s.size()) {
 				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
-				cell->get("\\A") = new_a;
-				cell->get("\\B") = new_b;
-				cell->get("\\S") = new_s;
+				cell->set("\\A", new_a);
+				cell->set("\\B", new_b);
+				cell->set("\\S", new_s);
 				if (new_s.size() > 1) {
 					cell->type = "$pmux";
 					cell->parameters["\\S_WIDTH"] = new_s.size();
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 8c281b342..1f8648c45 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -215,13 +215,19 @@ struct OptReduceWorker
 					log_signal(cell->get("\\B")), log_signal(cell->get("\\Y")));
 
 			cell->set("\\A", RTLIL::SigSpec());
-			for (auto &in_tuple : consolidated_in_tuples)
-				cell->get("\\A").append(in_tuple.at(0));
+			for (auto &in_tuple : consolidated_in_tuples) {
+				RTLIL::SigSpec new_a = cell->get("\\A");
+				new_a.append(in_tuple.at(0));
+				cell->set("\\A", new_a);
+			}
 
 			cell->set("\\B", RTLIL::SigSpec());
 			for (int i = 1; i <= cell->get("\\S").size(); i++)
-				for (auto &in_tuple : consolidated_in_tuples)
-					cell->get("\\B").append(in_tuple.at(i));
+				for (auto &in_tuple : consolidated_in_tuples) {
+					RTLIL::SigSpec new_b = cell->get("\\B");
+					new_b.append(in_tuple.at(i));
+					cell->set("\\B", new_b);
+				}
 
 			cell->parameters["\\WIDTH"] = RTLIL::Const(new_sig_y.size());
 			cell->set("\\Y", new_sig_y);
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 8412f929f..4f733a373 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -263,7 +263,7 @@ struct OptShareWorker
 					log("  Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
 					for (auto &it : cell->connections()) {
 						if (ct.cell_output(cell->type, it.first)) {
-							RTLIL::SigSpec other_sig = sharemap[cell]->connections()[it.first];
+							RTLIL::SigSpec other_sig = sharemap[cell]->get(it.first);
 							log("    Redirecting output %s: %s = %s\n", it.first.c_str(),
 									log_signal(it.second), log_signal(other_sig));
 							module->connect(RTLIL::SigSig(it.second, other_sig));