Removed RTLIL::SigSpec::expand() method

4 files changed, 39 insertions, 40 deletions

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 23fc48d5d..0be36606d 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -233,14 +233,12 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 			if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
 				del_wires.push_back(wire);
 			} else {
-				s1.expand();
-				s2.expand();
-				assert(s1.chunks().size() == s2.chunks().size());
+				assert(SIZE(s1) == SIZE(s2));
 				RTLIL::SigSig new_conn;
-				for (size_t i = 0; i < s1.chunks().size(); i++)
-					if (s1.chunks()[i] != s2.chunks()[i]) {
-						new_conn.first.append(s1.chunks()[i]);
-						new_conn.second.append(s2.chunks()[i]);
+				for (int i = 0; i < SIZE(s1); i++)
+					if (s1[i] != s2[i]) {
+						new_conn.first.append_bit(s1[i]);
+						new_conn.second.append_bit(s2[i]);
 					}
 				if (new_conn.first.size() > 0) {
 					new_conn.first.optimize();
@@ -257,9 +255,8 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
 		RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
 		if (!used_signals_nodrivers.check_any(sig)) {
 			std::string unused_bits;
-			sig.expand();
-			for (size_t i = 0; i < sig.chunks().size(); i++) {
-				if (sig.chunks()[i].wire == NULL)
+			for (int i = 0; i < SIZE(sig); i++) {
+				if (sig[i].wire == NULL)
 					continue;
 				if (!used_signals_nodrivers.check_any(sig)) {
 					if (!unused_bits.empty())
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 9b89291b1..ff139854f 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -458,21 +458,19 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 
 			RTLIL::SigSpec new_a, new_b;
-			a.expand(), b.expand();
 
-			assert(a.chunks().size() == b.chunks().size());
-			for (size_t i = 0; i < a.chunks().size(); i++) {
-				if (a.chunks()[i].wire == NULL && b.chunks()[i].wire == NULL && a.chunks()[i].data.bits[0] != b.chunks()[i].data.bits[0] &&
-						a.chunks()[i].data.bits[0] <= RTLIL::State::S1 && b.chunks()[i].data.bits[0] <= RTLIL::State::S1) {
+			assert(SIZE(a) == SIZE(b));
+			for (int i = 0; i < SIZE(a); i++) {
+				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(module, cell, "empty", "\\Y", new_y);
 					goto next_cell;
 				}
-				if (a.chunks()[i] == b.chunks()[i])
+				if (a[i] == b[i])
 					continue;
-				new_a.append(a.chunks()[i]);
-				new_b.append(b.chunks()[i]);
+				new_a.append(a[i]);
+				new_b.append(b[i]);
 			}
 
 			if (new_a.size() == 0) {
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 61147f67a..dfcd55126 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -36,7 +36,11 @@ struct OptMuxtreeWorker
 	SigMap assign_map;
 	int removed_count;
 
-	typedef std::pair<RTLIL::Wire*,int> bitDef_t;
+        struct bitDef_t : public std::pair<RTLIL::Wire*, int> {
+		bitDef_t() : std::pair<RTLIL::Wire*, int>(NULL, 0) { }
+		bitDef_t(const RTLIL::SigBit &bit) : std::pair<RTLIL::Wire*, int>(bit.wire, bit.offset) { }
+	};
+
 
 	struct bitinfo_t {
 		int num;
@@ -259,10 +263,8 @@ struct OptMuxtreeWorker
 	{
 		std::vector<int> results;
 		assign_map.apply(sig);
-		sig.expand();
-		for (auto &c : sig.chunks())
-			if (c.wire != NULL) {
-				bitDef_t bit(c.wire, c.offset);
+		for (auto &bit : sig)
+			if (bit.wire != NULL) {
 				if (bit2num.count(bit) == 0) {
 					bitinfo_t info;
 					info.num = bit2info.size();
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index 7ab7233c6..913855f48 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -44,46 +44,48 @@ struct OptReduceWorker
 		cells.erase(cell);
 
 		RTLIL::SigSpec sig_a = assign_map(cell->connections["\\A"]);
-		sig_a.sort_and_unify();
-		sig_a.expand();
+		std::set<RTLIL::SigBit> new_sig_a_bits;
 
-		RTLIL::SigSpec new_sig_a;
-		for (auto &chunk : sig_a.chunks())
+		for (auto &bit : sig_a.to_sigbit_set())
 		{
-			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S0) {
+			if (bit == RTLIL::State::S0) {
 				if (cell->type == "$reduce_and") {
-					new_sig_a = RTLIL::SigSpec(RTLIL::State::S0);
+					new_sig_a_bits.clear();
+					new_sig_a_bits.insert(RTLIL::State::S0);
 					break;
 				}
 				continue;
 			}
-			if (chunk.wire == NULL && chunk.data.bits[0] == RTLIL::State::S1) {
+			if (bit == RTLIL::State::S1) {
 				if (cell->type == "$reduce_or") {
-					new_sig_a = RTLIL::SigSpec(RTLIL::State::S1);
+					new_sig_a_bits.clear();
+					new_sig_a_bits.insert(RTLIL::State::S1);
 					break;
 				}
 				continue;
 			}
-			if (chunk.wire == NULL) {
-				new_sig_a.append(chunk);
+			if (bit.wire == NULL) {
+				new_sig_a_bits.insert(bit);
 				continue;
 			}
 
 			bool imported_children = false;
-			for (auto child_cell : drivers.find(chunk)) {
+			for (auto child_cell : drivers.find(bit)) {
 				if (child_cell->type == cell->type) {
 					opt_reduce(cells, drivers, child_cell);
-					if (child_cell->connections["\\Y"].extract(0, 1) == chunk)
-						new_sig_a.append(child_cell->connections["\\A"]);
-					else
-						new_sig_a.append(RTLIL::State::S0);
+					if (child_cell->connections["\\Y"][0] == bit) {
+						std::set<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->connections["\\A"]).to_sigbit_set();
+						new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
+					} else
+						new_sig_a_bits.insert(RTLIL::State::S0);
 					imported_children = true;
 				}
 			}
 			if (!imported_children)
-				new_sig_a.append(chunk);
+				new_sig_a_bits.insert(bit);
 		}
-		new_sig_a.sort_and_unify();
+
+		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
 
 		if (new_sig_a != sig_a || sig_a.size() != cell->connections["\\A"].size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));