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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 08:40:31 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:49:43 +0200 |
| commit | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch) | |
| tree | ed08831d07df4e799d881349c36acf76bf277791 /passes/opt | |
| parent | 260c19ec5a3adb292158658dd69a352b9325ab64 (diff) | |
| download | yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.gz yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.tar.bz2 yosys-a8d3a68971ccc4e47c54a906aae374a9a54b1415.zip | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 68fb2e72c..165bb25c9 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (auto &it : module->wires) { RTLIL::Wire *wire = it.second; for (int i = 0; i < wire->width; i++) { - RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1); + RTLIL::SigSpec s1 = RTLIL::SigSpec::grml(wire, i), s2 = assign_map(s1); if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires)) assign_map.add(s1); } |