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author | Clifford Wolf <clifford@clifford.at> | 2014-07-27 15:13:29 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-27 15:13:29 +0200 |
commit | 77a1462f2d6602d5c46a2a15ca534550ec5bb9a4 (patch) | |
tree | 85ad5a725d8c998ee419271727114e8098b10c30 /passes/opt | |
parent | d07a871d35401b6b8628dd3f1df3b91149e827d5 (diff) | |
download | yosys-77a1462f2d6602d5c46a2a15ca534550ec5bb9a4.tar.gz yosys-77a1462f2d6602d5c46a2a15ca534550ec5bb9a4.tar.bz2 yosys-77a1462f2d6602d5c46a2a15ca534550ec5bb9a4.zip |
Fixed bug in opt_clean
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 21bda6e4e..76a905b2c 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -251,7 +251,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool for (int i = 0; i < SIZE(sig); i++) { if (sig[i].wire == NULL) continue; - if (!used_signals_nodrivers.check_any(sig)) { + if (!used_signals_nodrivers.check_any(sig[i])) { if (!unused_bits.empty()) unused_bits += " "; unused_bits += stringf("%zd", i); |