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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
| commit | f092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch) | |
| tree | 2f09add560746030249fe333e551de2f113bccdb /passes/opt | |
| parent | bf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff) | |
| download | yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.gz yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.bz2 yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.zip | |
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'passes/opt')
| -rw-r--r-- | passes/opt/opt_const.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index a13bb09cb..9af1e6bdf 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -209,7 +209,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo for (auto cell : module->cells()) if (design->selected(module, cell) && cell->type[0] == '$') { - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && + if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\A").size() == 1 && cell->getPort("\\Y").size() == 1) invert_map[assign_map(cell->getPort("\\Y"))] = assign_map(cell->getPort("\\A")); if (ct_combinational.cell_known(cell->type)) @@ -371,9 +371,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo } } - if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && + if ((cell->type == "$_NOT_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 && invert_map.count(assign_map(cell->getPort("\\A"))) != 0) { - cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str()); + cover_list("opt.opt_const.invert.double", "$_NOT_", "$not", "$logic_not", cell->type.str()); replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A")))); goto next_cell; } @@ -389,7 +389,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo goto next_cell; } - if (cell->type == "$_INV_") { + if (cell->type == "$_NOT_") { RTLIL::SigSpec input = cell->getPort("\\A"); assign_map.apply(input); if (input.match("1")) ACTION_DO_Y(0); @@ -463,7 +463,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo if (input.match("01 ")) ACTION_DO("\\Y", input.extract(0, 1)); if (input.match("10 ")) { cover("opt.opt_const.mux_to_inv"); - cell->type = "$_INV_"; + cell->type = "$_NOT_"; cell->setPort("\\A", input.extract(0, 1)); cell->unsetPort("\\B"); cell->unsetPort("\\S"); @@ -648,7 +648,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->parameters.erase("\\WIDTH"); cell->type = "$not"; } else - cell->type = "$_INV_"; + cell->type = "$_NOT_"; OPT_DID_SOMETHING = true; did_something = true; goto next_cell; |