iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Optimize shift ops with constant rhs in opt_const	Clifford Wolf	2014-08-24	1	-0/+35
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*	Added some additional log messages to opt_const	Clifford Wolf	2014-08-24	1	-1/+10
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*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17	1	-1/+1
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*	Added "opt -fast"	Clifford Wolf	2014-08-16	1	-19/+45
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-6/+6
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*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-2/+2
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14	3	-3/+2
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*	Fixed a performance bug in opt_reduce	Clifford Wolf	2014-08-02	1	-2/+6
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	4	-29/+30
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*	Replaced sha1 implementation	Clifford Wolf	2014-08-01	2	-7/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	5	-170/+170
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-7/+9
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	5	-7/+2
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-2/+2
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*	Fixed bug in opt_clean	Clifford Wolf	2014-07-27	1	-1/+1
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-29/+54
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*	Fixed a bug in opt_clean and some RTLIL API usage cleanups	Clifford Wolf	2014-07-27	2	-13/+14
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-12/+11
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-7/+7
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	6	-18/+18
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	5	-9/+9
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+10
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-1/+1
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*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26	1	-2/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	4	-24/+32
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	6	-195/+195
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-195/+195
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	6	-22/+9
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*	Fixed memory corruption in "opt_reduce" pass	Clifford Wolf	2014-07-25	1	-5/+7
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-9/+4
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*	Added cover() calls to opt_const	Clifford Wolf	2014-07-24	1	-9/+45
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	2	-4/+0
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	4	-40/+39
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	1	-7/+2
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	6	-89/+89
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	6	-89/+89
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*	Added "opt_const -keepdc"	Clifford Wolf	2014-07-21	2	-15/+168
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*	Added mul to mux conversion to "opt_const -fine"	Clifford Wolf	2014-07-21	1	-0/+55
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*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21	3	-15/+144
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*	Added opt_const support for simple identities	Clifford Wolf	2014-07-21	1	-0/+69
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*	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	Clifford Wolf	2014-07-18	1	-0/+15
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*	Improved opt_reduce handling of mem wr_en mux bits	Clifford Wolf	2014-07-17	1	-5/+18
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*	improved opt_reduce for $mem/$memwr WR_EN multiplexers	Clifford Wolf	2014-07-16	1	-0/+80
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*	Fixed bug in opt_reduce (see vloghammer issue_044)	Clifford Wolf	2014-05-12	1	-1/+4
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*	Fixed performance problem in opt_mux with nets driven by many conflicting ↵	Clifford Wolf	2014-03-19	1	-1/+6
\| \| \| \|	drivers
*	Fixed undef handling in opt_reduce	Clifford Wolf	2014-03-06	1	-2/+2
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*	Fixed const folding of $bu0 cells	Clifford Wolf	2014-02-27	1	-0/+1
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*	Fixed bug (typo) in passes/opt/opt_const.cc	Clifford Wolf	2014-02-22	1	-1/+1
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