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* Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-171-0/+3
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* opt_expr: Optimizations for `$bweqx` and `$bwmux`Jannis Harder2022-11-301-0/+63
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* opt_expr: Fix shift/shiftx optimizationsJannis Harder2022-11-301-3/+3
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* opt_expr: Constant fold mux, pmux, bmux, demux, eqx, nex cellsJannis Harder2022-11-291-0/+33
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* opt_expr: Optimize bitwise logic ops with one fully const inputJannis Harder2022-11-291-0/+81
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* Consistent $mux undef handlingJannis Harder2022-10-241-1/+1
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Fitting help messages to 80 character widthKrystalDelusion2022-08-241-4/+7
| | | | | | | | | Uses the regex below to search (using vscode): ^\t\tlog\("(.{10,}(?<!\\n)|.{81,}\\n)"\); Finds any log messages double indented (which help messages are) and checks if *either* there are is no newline character at the end, *or* the number of characters before the newline is more than 80.
* wreduce: Keep more x-bits with -keepdcJannis Harder2022-08-161-4/+4
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* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+2
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* opt_reduce: Fix use-after-free.Marcelina Kościelnicka2022-07-231-4/+2
| | | | Fixes #3418.
* opt_dff: With -keepdc, never turn undef init vals into const driversJannis Harder2022-06-291-5/+17
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* opt_ffinv: Fix use after free.Marcelina Kościelnicka2022-06-131-3/+6
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* wreduce: Introduce -mux_undef option (aligned with opt_expr).Marcelina Kościelnicka2022-06-081-1/+9
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* opt_ffinv: Harden against simple ff/inv loop.Marcelina Kościelnicka2022-06-071-0/+4
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* opt_ffinv: Use ModIndex instead of ModWalker.Marcelina Kościelnicka2022-05-171-50/+53
| | | | This avoids using out-of-data index information.
* Add opt_ffinv pass.Marcelina Kościelnicka2022-05-132-0/+256
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* opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-071-13/+143
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* opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-012-2/+21
| | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.
* opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-301-60/+337
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* opt_dff: Don't mutate muxes while ModWalker is active.Marcelina Kościelnicka2022-01-281-98/+112
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* opt_dff: fix sequence point copy paste bugAustin Seipp2022-01-041-1/+1
| | | | | | | | | | | | | | | | Newer GCCs emit the following warning for opt_dff: passes/opt/opt_dff.cc:560:17: warning: operation on ‘ff.Yosys::FfData::has_clk’ may be undefined [-Wsequence-point] 560 | ff.has_clk = ff.has_ce = ff.has_clk = false; | ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Which is correct: the order of whether the read or write of has_clk occurs first is undefined since there is no sequence point between them. This is almost certainly just a typo/copy paste error and objectively wrong, so just fix it. Signed-off-by: Austin Seipp <aseipp@pobox.com>
* opt_mem_priority: Fix non-ascii char in help message.Marcelina Kościelnicka2021-12-091-1/+1
| | | | This is a fixed version of #3072.
* gowin: widelut support (#3042)Pepijn de Vos2021-11-061-2/+8
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-071-10/+10
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-021-2/+12
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* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-021-90/+139
| | | | | | | | | | - *_en is split into *_ce (clock enable) and *_aload (async load aka latch gate enable), so both can be present at once - has_d is removed - has_gclk is added (to have a clear marker for $ff) - d_is_const and val_d leftovers are removed - async2sync, clk2fflogic, opt_dff are updated to operate correctly on FFs with async load
* opt_merge: Remove and reinsert init when connecting nets.Marcelina Kościelnicka2021-08-221-3/+4
| | | | | | | | Mutating the SigMap by adding a new connection will throw off FfInitVals index. Work around this by removing the relevant init values from index whenever we connect nets, then re-add the new init value. Should fix #2920.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-0/+24
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-142-0/+108
| | | | If all of us are wide, then none of us are!
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-132-0/+110
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-115-9/+12
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* kernel/mem: Introduce transparency masks.Marcelina Kościelnicka2021-08-111-1/+3
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* Refactor common parts of SAT-using optimizations into a helper.Marcelina Kościelnicka2021-08-092-89/+30
| | | | | | | | | | | | | This also aligns the functionality: - in all cases, the onehot attribute is used to create appropriate constraints (previously, opt_dff didn't do it at all, and share created one-hot constraints based on $pmux presence alone, which is unsound) - in all cases, shift and mul/div/pow cells are now skipped when importing the SAT problem (previously only memory_share did this) — this avoids creating clauses for hard cells that are unlikely to help with proving the UNSATness needed for optimization
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-081-27/+8
| | | | Partial #2920 fix.
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-23/+30
| | | | Fixes #2061.
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-282-2/+2
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* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-271-3/+22
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* opt_muxtree: Update port_off and port_idx even for constant bitsgatecat2021-06-111-17/+16
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-122/+85
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* opt_expr: Optimize div/mod by const 1.Marcelina Kościelnicka2021-06-091-4/+4
| | | | | | | | Turns out the code for div by a power of 2 is already almost capable of optimizing this to a shift-by-0 or and-with-0, which will be further folded into nothingness; let's beef it up to handle div by 1 as well. Fixes #2820.
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0817-17/+17
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/mem: Add sub_addr helpers.Marcelina Kościelnicka2021-05-261-6/+2
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* opt_mem: Add reset/init value support.Marcelina Kościelnicka2021-05-251-0/+12
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* opt_mem_feedback: Respect write port priority.Marcelina Kościelnicka2021-05-251-0/+15
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* opt_mem_feedback: Add wide port support.Marcelina Kościelnicka2021-05-251-14/+24
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* opt_mem_feedback: Rewrite feedback path finding logic.Marcelina Kościelnicka2021-05-241-115/+130
| | | | Fixes #2766.
* opt_mem_feedback: Convert to Mem helpers.Marcelina Kościelnicka2021-05-241-49/+28
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* memory_share: Split off feedback path finding as a separate pass.Marcelina Kościelnicka2021-05-232-0/+334
| | | | | memory_share is actually three passes in a trenchcoat. Split off the one that has the least in common with the other two as a separate pass.
* opt_mem: Remove write ports with const-0 EN.Marcelina Kościelnicka2021-05-231-0/+12
| | | | Fixes #2765.
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