| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | kernel: pass-by-value into Design::scratchpad_set_string() too | Eddie Hung | 2020-03-27 | 2 | -3/+3 |
| | * | | kernel: const Wire* overload -> Wire* !!! | Eddie Hung | 2020-03-26 | 1 | -1/+1 |
| | * | | kernel: Cell::set{Port,Param}() to pass by value, but use std::move | Eddie Hung | 2020-03-26 | 2 | -7/+7 |
| | * | | kernel: SigSpec copies to not trigger pack() | Eddie Hung | 2020-03-18 | 2 | -34/+5 |
| | * | | kernel: more pass by const ref, more speedups | Eddie Hung | 2020-03-18 | 3 | -361/+355 |
| | * | | kernel: speedup | Eddie Hung | 2020-03-18 | 1 | -30/+23 |
| | * | | kernel: use const reference for SigSet too | Eddie Hung | 2020-03-17 | 1 | -18/+18 |
| | * | | kernel: fix DeleteWireWorker | Eddie Hung | 2020-03-17 | 1 | -9/+4 |
| | * | | kernel: SigSpec use more const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-13 | 2 | -38/+52 |
| | * | | kernel: optimise Module::remove(const pool<RTLIL::Wire*>() | Eddie Hung | 2020-03-12 | 2 | -10/+9 |
| | * | | kernel: SigPool to use const& + overloads to prevent implicit SigSpec | Eddie Hung | 2020-03-12 | 1 | -19/+25 |
| * | | | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup | Eddie Hung | 2020-04-01 | 1 | -10/+3 |
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| | * | | | kernel: share a single CellTypes within a pass | Eddie Hung | 2020-03-18 | 1 | -10/+3 |
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| * | / | Clean up pseudo-private member usage in `kernel/yosys.cc`. | Alberto Gonzalez | 2020-04-01 | 1 | -14/+13 |
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| * | | Add support for SystemVerilog-style `define to Verilog frontend | Rupert Swarbrick | 2020-03-27 | 2 | -1/+6 |
| * | | Update Copyright | Claire Wolf | 2020-03-16 | 1 | -1/+1 |
| * | | License: bump year and add title | Waldir Pimenta | 2020-03-14 | 1 | -1/+1 |
| * | | exclude clang from checking | Miodrag Milanovic | 2020-03-13 | 1 | -1/+1 |
| * | | Add YS_ prefix to macros, add explanation and apply to older version as well | Miodrag Milanovic | 2020-03-13 | 3 | -20/+23 |
| * | | Use boost xpressive for gcc 4.8 | Miodrag Milanovic | 2020-03-13 | 3 | -23/+29 |
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| * | Fix compilation for emcc | jiegec | 2020-03-11 | 2 | -1/+4 |
| * | Add ScriptPass::run_nocheck and use for abc9 | David Shah | 2020-03-09 | 2 | -0/+13 |
| * | Merge pull request #1718 from boqwxp/precise_locations | Claire Wolf | 2020-03-03 | 1 | -2/+0 |
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| | * | Closes #1717. Add more precise Verilog source location information to AST and... | Alberto Gonzalez | 2020-02-23 | 1 | -2/+0 |
| * | | Small fixes | Eddie Hung | 2020-02-27 | 1 | -2/+2 |
| * | | Fixes for older compilers | Eddie Hung | 2020-02-27 | 1 | -1/+8 |
| * | | Make TimingInfo::TimingInfo(SigBit) constructor explicit | Eddie Hung | 2020-02-27 | 1 | -4/+5 |
| * | | TimingInfo: index by (port_name,offset) | Eddie Hung | 2020-02-27 | 1 | -9/+19 |
| * | | Fix spacing | Eddie Hung | 2020-02-27 | 1 | -50/+50 |
| * | | Get rid of (* abc9_{arrival,required} *) entirely | Eddie Hung | 2020-02-27 | 1 | -3/+4 |
| * | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 1 | -1/+4 |
| * | | abc9_ops: use TimingInfo for -prep_{lut,box} too | Eddie Hung | 2020-02-27 | 1 | -18/+2 |
| * | | abc9_ops: add and use new TimingInfo struct | Eddie Hung | 2020-02-27 | 1 | -0/+173 |
| * | | Merge pull request #1705 from YosysHQ/logger_pass | Miodrag Milanović | 2020-02-26 | 3 | -2/+100 |
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| | * | Remove duplicate warning detection | Miodrag Milanovic | 2020-02-23 | 1 | -0/+6 |
| | * | Handle expect no warnings together with expected | Miodrag Milanovic | 2020-02-22 | 3 | -4/+12 |
| | * | Prevent double error message | Miodrag Milanovic | 2020-02-17 | 1 | -1/+3 |
| | * | Option to expect no warnings | Miodrag Milanovic | 2020-02-17 | 3 | -0/+5 |
| | * | No new error if already failing | Miodrag Milanovic | 2020-02-17 | 1 | -1/+2 |
| | * | remove whitespace | Miodrag Milanovic | 2020-02-14 | 1 | -1/+1 |
| | * | Add expect option to logger command | Miodrag Milanovic | 2020-02-14 | 3 | -2/+78 |
| * | | specify: system timing checks to accept min:typ:max triple | Eddie Hung | 2020-02-13 | 1 | -2/+6 |
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| * | Merge pull request #1659 from YosysHQ/clifford/experimental | Claire Wolf | 2020-01-29 | 5 | -3/+55 |
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| | * | Improve logging use of experimental features | Claire Wolf | 2020-01-28 | 3 | -4/+8 |
| | * | Add log_experimental() and experimental() API and "yosys -x" | Claire Wolf | 2020-01-27 | 5 | -3/+51 |
| * | | Add and use SigSpec::reverse() | Eddie Hung | 2020-01-28 | 1 | -0/+2 |
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| * | Merge pull request #1613 from porglezomp-misc/version-flag-alias | Claire Wolf | 2020-01-27 | 1 | -0/+6 |
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| | * | Add --version and -version as aliases for -V | Cassie Jones | 2020-01-05 | 1 | -0/+6 |
| * | | As before, only display MEM if Linux or FreeBSD | Eddie Hung | 2020-01-14 | 1 | -3/+7 |
| * | | print_stats footer to return peak memory, option for including children | Eddie Hung | 2020-01-14 | 1 | -28/+12 |
