iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add $_ANDNOT_ and $_ORNOT_ gates	Clifford Wolf	2017-05-17	1	-26/+30
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*	Add $live and $fair cell types, add support for s_eventually keyword	Clifford Wolf	2017-02-25	1	-1/+17
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*	Add $cover cell type and SVA cover() support	Clifford Wolf	2017-02-04	1	-1/+9
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*	Fix RTLIL::Memory::start_offset initialization	Clifford Wolf	2017-01-25	1	-0/+1
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*	Bugfix in RTLIL::SigSpec::remove2()	Clifford Wolf	2016-12-31	1	-3/+4
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*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	1	-0/+2
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*	Added $anyseq cell type	Clifford Wolf	2016-10-14	1	-1/+10
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*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	1	-0/+25
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*	Improvements in assertpmux	Clifford Wolf	2016-09-07	1	-0/+16
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*	Removed $aconst cell type	Clifford Wolf	2016-08-30	1	-1/+1
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*	Removed $predict again	Clifford Wolf	2016-08-28	1	-9/+1
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*	Fixed handling of transparent bram rd ports on ROMs	Clifford Wolf	2016-08-27	1	-0/+1
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*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	1	-0/+6
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*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	1	-0/+6
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	1	-2/+2
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	1	-8/+17
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*	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-1/+1
\| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
*	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	1	-0/+2
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*	Improved support for $sop cells	Clifford Wolf	2016-06-17	1	-1/+1
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*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	1	-0/+9
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*	Added addBufGate module method	Clifford Wolf	2016-02-02	1	-0/+1
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*	rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+31
\| \| \| \| \| \| \| \|	Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop.
*	rtlil: speed up SigSpec::sort_and_unify()	Rick Altherr	2016-01-31	1	-1/+11
\| \| \| \| \| \| \| \| \| \|	std::set<> internally is often a red-black tree which is fairly expensive to create but fast to lookup. In the case of sort_and_unify(), a set<> is constructed as a temporary object to attempt to speed up lookups. Being a temporarily, however, the cost of creation far outweights the lookup improvement and is a net performance loss. Instead, sort the vector<> that already exists and then apply std::unique().
*	rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-6/+14
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*	rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)	Rick Altherr	2016-01-31	1	-2/+29
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*	rtlil: rewrite remove2() to avoid copying	Rick Altherr	2016-01-30	1	-45/+18
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*	rtlil: duplicate remove2() for std::set<>	Rick Altherr	2016-01-29	1	-0/+39
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*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25	1	-14/+14
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*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24	1	-12/+11
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*	Fixed driver conflict handling (various cmds)	Clifford Wolf	2015-10-24	1	-3/+12
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*	Fixed handling of driver-driver conflicts in wreduce	Clifford Wolf	2015-10-24	1	-0/+4
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-0/+2
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*	Cosmetic fix in Module::addLut()	Clifford Wolf	2015-09-18	1	-4/+4
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*	Added $tribuf and $_TBUF_ cell types	Clifford Wolf	2015-08-16	1	-0/+20
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*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11	1	-0/+4
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*	Added WORDS parameter to $meminit	Clifford Wolf	2015-07-31	1	-1/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-5/+5
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*	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30	1	-0/+7
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*	Added "rename -top new_name"	Clifford Wolf	2015-06-17	1	-0/+15
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*	Fixed cstr_buf for std::string with small string optimization	Clifford Wolf	2015-06-11	1	-1/+1
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*	Fixed "avail_parameters" handling in module clone/copy	Clifford Wolf	2015-06-08	1	-0/+2
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*	Added $eq/$neq -> $logic_not/$reduce_bool optimization	Clifford Wolf	2015-04-29	1	-0/+15
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*	Improved attributes API and handling of "src" attributes	Clifford Wolf	2015-04-24	1	-0/+40
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*	Avoid parameter values with size 0 ($mem cells)	Clifford Wolf	2015-04-05	1	-5/+5
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*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05	1	-0/+4
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*	Added $assume cell type	Clifford Wolf	2015-02-26	1	-0/+7
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-0/+1
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*	Added $meminit cell type	Clifford Wolf	2015-02-14	1	-0/+9
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*	Added SigSpec::has_const()	Clifford Wolf	2015-02-08	1	-0/+12
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*	Added cell->known(), cell->input(portname), cell->output(portname)	Clifford Wolf	2015-02-07	1	-0/+34
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