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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:04:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-26 18:04:10 +0100 |
| commit | b005eedf369bc60ce5f7cba9a0db4694f22a360f (patch) | |
| tree | 1f8454d41443fbb2c3a4f7f2b72cee5fd2482723 /kernel/rtlil.cc | |
| parent | 27a918eadf11cfe6cfe0eead022c8ff3336a855e (diff) | |
| download | yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.tar.gz yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.tar.bz2 yosys-b005eedf369bc60ce5f7cba9a0db4694f22a360f.zip | |
Added $assume cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c10261b23..adf89a245 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -941,6 +941,13 @@ namespace { return; } + if (cell->type == "$assume") { + port("\\A", 1); + port("\\EN", 1); + check_expected(); + return; + } + if (cell->type == "$equiv") { port("\\A", 1); port("\\B", 1); |