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* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
* Fix typoEddie Hung2019-09-301-1/+1
* Avoid work in replace() if rules empty.Henner Zeller2019-09-291-0/+2
* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-96/+96
* Add YOSYS_NO_IDS_REFCNT configuration macroClifford Wolf2019-08-111-1/+3
* Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)Clifford Wolf2019-08-111-578/+585
* More improvements and cleanups in IdString subsystemClifford Wolf2019-08-111-0/+2
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
* stoi -> atoiEddie Hung2019-08-071-3/+3
* Fix typosEddie Hung2019-08-061-2/+2
* Use std::stoi instead of atoi(<str>.c_str())Eddie Hung2019-08-061-3/+3
* Use IdString::begins_with()Eddie Hung2019-08-061-4/+4
* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+2
* In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
* Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-151-7/+22
* Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
* Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-031-1/+1
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| * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
* | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
* | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
* | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-231-0/+15
* | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
* | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
* | Add specify parserClifford Wolf2019-04-231-0/+10
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* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+97
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| * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-3/+31
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| * | added some checks if python is enabled to make sure everything compiles if py...Benedikt Tutzer2018-08-201-4/+2
| * | Added Wrappers for:Benedikt Tutzer2018-08-131-1/+31
| * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-0/+14
| * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
| * | multiple designs can now exist independent from each other. Cells/Wires/Modul...Benedikt Tutzer2018-07-091-0/+55
* | | Add "wbflip" commandClifford Wolf2019-04-201-2/+5
* | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-3/+3
* | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+24
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* | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-1/+1
* | Add fmcombine passClifford Wolf2019-03-151-2/+2
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+2
* | Add FF support to wreduceClifford Wolf2019-02-201-0/+3
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+10
* | Documentation improvements etc.Ruben Undheim2018-10-131-3/+1
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+15
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-1/+21
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+3
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+11
* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+15
* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-56/+91
* Update more stuff to use get_src_attribute() and set_src_attribute()Clifford Wolf2017-09-011-1/+1