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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:52:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | e807e88b607834170692f56a5538b89fd4175a36 (patch) | |
| tree | 9b94e7a27334a7be697146f9ff6702e81b58fd73 /kernel/rtlil.cc | |
| parent | 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 (diff) | |
| download | yosys-e807e88b607834170692f56a5538b89fd4175a36.tar.gz yosys-e807e88b607834170692f56a5538b89fd4175a36.tar.bz2 yosys-e807e88b607834170692f56a5538b89fd4175a36.zip | |
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9e06b8323..4522b0a08 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1199,10 +1199,10 @@ namespace { param_bool("\\SRC_DST_PEN"); param_bool("\\SRC_DST_POL"); param("\\T_RISE_MIN"); - param("\\T_RISE_AVG"); + param("\\T_RISE_TYP"); param("\\T_RISE_MAX"); param("\\T_FALL_MIN"); - param("\\T_FALL_AVG"); + param("\\T_FALL_TYP"); param("\\T_FALL_MAX"); port("\\EN", 1); port("\\SRC", param("\\SRC_WIDTH")); |