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authorClifford Wolf <clifford@clifford.at>2019-04-05 17:31:49 +0200
committerClifford Wolf <clifford@clifford.at>2019-04-05 17:31:49 +0200
commitdfb242c905ff10bb4038f080aeb74a820e8fbd00 (patch)
tree7a900803745f7ab020ad801bfa4b4b8c1f2877c7 /kernel/rtlil.cc
parent75ca06526a29dfac447265a52014305fb96d7ebf (diff)
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Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r--kernel/rtlil.cc24
1 files changed, 24 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b3214579d..9ae20a317 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -641,6 +641,30 @@ RTLIL::Module::~Module()
delete it->second;
}
+void RTLIL::Module::makeblackbox()
+{
+ pool<RTLIL::Wire*> delwires;
+
+ for (auto it = wires_.begin(); it != wires_.end(); ++it)
+ if (!it->second->port_input && !it->second->port_output)
+ delwires.insert(it->second);
+
+ for (auto it = memories.begin(); it != memories.end(); ++it)
+ delete it->second;
+ memories.clear();
+
+ for (auto it = cells_.begin(); it != cells_.end(); ++it)
+ delete it->second;
+ cells_.clear();
+
+ for (auto it = processes.begin(); it != processes.end(); ++it)
+ delete it->second;
+ processes.clear();
+
+ remove(delwires);
+ set_bool_attribute("\\blackbox");
+}
+
void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
{
log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));