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| author | Henner Zeller <h.zeller@acm.org> | 2019-09-29 00:17:40 -0700 |
|---|---|---|
| committer | Henner Zeller <h.zeller@acm.org> | 2019-09-29 00:17:40 -0700 |
| commit | 8c2b4f0a50678f949418b7b7329550615fadde83 (patch) | |
| tree | a16bed0943ca5152a7aaf04618d2353aafd40e82 /kernel/rtlil.cc | |
| parent | c372e7baf9c48d41ebdbea4486a72e8dfaaddd3d (diff) | |
| download | yosys-8c2b4f0a50678f949418b7b7329550615fadde83.tar.gz yosys-8c2b4f0a50678f949418b7b7329550615fadde83.tar.bz2 yosys-8c2b4f0a50678f949418b7b7329550615fadde83.zip | |
Avoid work in replace() if rules empty.
This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382.
Signed-off-by: Henner Zeller <h.zeller@acm.org>
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d380135b..17be28f78 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); @@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); |