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* Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-301-0/+36
| | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+17
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Assorted microoptimization speedups in core data structures.Marcelina Kościelnicka2022-07-271-120/+61
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* Add a check for packed memory MEMID uniquenessMarcelina Kościelnicka2022-06-131-0/+10
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* Use compiler-generated default constructor for RTLIL::Const::ConstHenner Zeller2022-06-091-9/+1
| | | | | | No need for a manual implementation. While at it: have the constructor that takes a string take a const string reference instead to avoid a copy.
* Add some more reserve calls to RTLIL::ConstNotAFile2022-03-251-0/+5
| | | | This results in a slight ~0.22% total speedup synthesizing vexriscv
* Add $bmux and $demux cells.Marcelina Kościelnicka2022-01-281-2/+45
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* sta: very crude static timing analysis passLofty2021-11-251-0/+29
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+5
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-251-2/+2
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+110
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* Add additional check to SigSpecClaire Xenia Wolf2021-09-101-4/+12
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | This code now takes the AST nodes of type AST_BIND and generates a representation in the RTLIL for them. This is a little tricky, because a binding of the form: bind baz foo_t foo_i (.arg (1 + bar)); means "make an instance of foo_t called foo_i, instantiate it inside baz and connect the port arg to the result of the expression 1+bar". Of course, 1+bar needs a cell for the addition. Where should that cell live? With this patch, the Binding structure that represents the construct is itself an AST::AstModule module. This lets us put the adder cell inside it. We'll pull the contents out and plonk them into 'baz' when we actually do the binding operation as part of the hierarchy pass. Of course, we don't want RTLIL::Binding to contain an AST::AstModule (since kernel code shouldn't depend on a frontend), so we define RTLIL::Binding as an abstract base class and put the AST-specific code into an AST::Binding subclass. This is analogous to the AST::AstModule class.
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-2/+68
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-1/+11
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* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-1/+31
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* Simplify some RTLIL destructorsRupert Swarbrick2021-06-141-10/+10
| | | | | No change in behaviour, but use range-based for loops instead of iterators.
* opt_expr: Fix mul/div/mod by POT patterns to support >= 32 bits.Marcelina Kościelnicka2021-06-091-0/+33
| | | | | The previous code, in addition to being needlessly limitted to 32 bits in the first place, also had UB for the 31th bit (doing 1 << 31).
* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* kernel/rtlil: Extract some helpers for checking memory cell types.Marcelina Kościelnicka2021-05-221-0/+10
| | | | | | There will soon be more (versioned) memory cells, so handle passes that only care if a cell is memory-related by a simple helper call instead of a hardcoded list.
* rtlil: add const accessors for modules, wires, and cellsZachary Snow2021-03-251-0/+5
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* blackbox: Include whiteboxed modulesgatecat2021-03-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* rtlil: Disallow 0-width chunks in SigSpec.Marcelina Kościelnicka2021-03-151-18/+49
| | | | | | | | | Among other problems, this also fixes equality comparisons between SigSpec by enforcing a canonical form. Also fix another minor issue with possible non-canonical SigSpec. Fixes #2623.
* Add support for memory writes in processes.Marcelina Kościelnicka2021-03-081-0/+1
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* Replace assert in addModule with more useful error messageDan Ravensloft2021-03-061-1/+2
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* bugpoint: add -wires option.whitequark2020-12-071-1/+1
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-2/+2
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-1/+5
| | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-231-0/+193
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* Add new builtin FF typesMarcelina Kościelnicka2020-06-231-47/+224
| | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-091-2/+10
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+16
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* RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.whitequark2020-06-081-2/+2
| | | | | The only difference in behavior is that this removes the attribute when the pool becomes empty.
* Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-081-0/+12
|\ | | | | Split `flatten` from `techmap` and simplify it
| * RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-041-0/+12
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* | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+2
|\ \ | |/ |/| Preserve 'signed'-ness of a verilog wire through RTLIL
| * Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+2
| | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | Add flooring division operatorXiretza2020-05-281-1/+2
| | | | | | | | | | | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor.
* | Add flooring modulo operatorXiretza2020-05-281-1/+2
|/ | | | | | | | | | | The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $modfloor cell provides this flooring modulo (also known as "remainder" in several languages, but this name is ambiguous). This commit also fixes the handling of $mod in opt_expr, which was previously optimized as if it was $modfloor.
* kernel: Cell::getParam() to throw exception again if not foundEddie Hung2020-04-221-3/+2
| | | | As it did before #1945
* Use default parameter value in getParamMarcelina Kościelnicka2020-04-211-1/+10
| | | | Fixes #1822.
* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+2
| | | | Fixes #1819, #1820.
* rtlil: add AttrObject::has_attribute.whitequark2020-04-161-0/+5
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* rtlil: add AttrObject::{get,set}_string_attribute.whitequark2020-04-161-17/+17
| | | | And make {get,set}_src_attribute use those functions.
* Merge pull request #1927 from YosysHQ/eddie/design_remove_assertEddie Hung2020-04-161-0/+1
|\ | | | | kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
| * kernel: Design::remove(RTLIL::Module *) to check refcount_modules_Eddie Hung2020-04-141-0/+1
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* | kernel: Module::makeblackbox() to clear connections tooEddie Hung2020-04-131-0/+2
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* Merge pull request #1858 from YosysHQ/eddie/fix1856Eddie Hung2020-04-091-1/+1
|\ | | | | kernel: include "kernel/constids.inc"
| * kernel: include "kernel/constids.inc" instead of "constids.inc"Eddie Hung2020-04-091-1/+1
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* | [NFCI] Deduplicate builtin FF cell types listMarcelina Kościelnicka2020-04-091-0/+47
|/ | | | | | | | | A few passes included the same list of FF cell types. Make it a global const instead. The zinit pass also seems to include a list like that, but given that it seems to be completely broken at the time (see #1568 discussion), I'm going to pretend I didn't see that.
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