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* substr() -> compare()Eddie Hung2019-08-071-2/+2
* RTLIL::S{0,1} -> State::S{0,1}Eddie Hung2019-08-071-6/+6
* Use State::S{0,1}Eddie Hung2019-08-061-2/+2
* Make liberal use of IdString.in()Eddie Hung2019-08-061-1/+1
* Add $_NMUX_, add "abc -g cmos", add proper cmos cell costsClifford Wolf2019-08-061-0/+14
* Merge pull request #1203 from whitequark/write_verilog-zero-width-valuesClifford Wolf2019-07-181-1/+2
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| * write_verilog: dump zero width constants correctly.whitequark2019-07-161-1/+2
* | Remove old $pmux_safe code from write_verilogClifford Wolf2019-07-171-5/+4
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* Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmarkClifford Wolf2019-07-111-2/+8
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| * write_verilog: write RTLIL::Sa aka - as Verilog ?.whitequark2019-07-091-2/+8
* | write_verilog: fix placement of case attributes. NFC.whitequark2019-07-091-3/+2
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* verilog_backend: dump attributes on SwitchRule.whitequark2019-07-081-0/+1
* verilog_backend: dump attributes on CaseRule, as comments.whitequark2019-07-081-6/+10
* Fix handling of partial init attributes in write_verilog, fixes #997Clifford Wolf2019-05-071-1/+2
* Improve write_verilog specify supportClifford Wolf2019-05-041-15/+71
* Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
* Add $specify2/$specify3 support to write_verilogClifford Wolf2019-04-231-0/+47
* Add support for $assert/$assume/$cover to write_verilogClifford Wolf2019-04-231-0/+10
* Add support for zero-width signals to Verilog back-end, fixes #948Clifford Wolf2019-04-221-0/+8
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-1/+1
* Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-0/+4
* Add "write_verilog -siminit"Clifford Wolf2019-02-281-2/+11
* Instead of INIT param on cells, use initial statement with hier ref asEddie Hung2019-02-171-18/+13
* Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-171-38/+41
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| * write_verilog: correctly emit asynchronous transparent ports.whitequark2019-01-291-38/+41
* | Remove check for cell->name[0] == '$'Eddie Hung2019-02-061-1/+1
* | RefactorEddie Hung2019-02-061-21/+5
* | write_verilog to cope with init attr on q when -noexprEddie Hung2019-02-061-2/+32
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* Merge pull request #800 from whitequark/write_verilog_tribufClifford Wolf2019-01-271-0/+12
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| * write_verilog: write $tribuf cell as ternary.whitequark2019-01-271-0/+12
* | write_verilog: escape names that match SystemVerilog keywords.whitequark2019-01-271-0/+27
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* Fix handling of $shiftx in Verilog back-endClifford Wolf2019-01-151-3/+6
* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
* write_verilog: handle the $shift cell.whitequark2018-12-161-0/+29
* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-1/+1
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| * write_verilog: add a missing newline.whitequark2018-12-161-1/+1
* | write_verilog: correctly map RTLIL `sync init`.whitequark2018-12-071-0/+2
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* adding offset info to memoriesrafaeltp2018-10-181-1/+1
* adding offset info to memoriesrafaeltp2018-10-181-2/+3
* Fixed typo in "verilog_write" help messageacw12512018-09-181-3/+3
* Add $lut support to Verilog back-endClifford Wolf2018-09-061-0/+13
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Add $dlatch support to write_verilogClifford Wolf2018-04-221-0/+38
* Add $shiftx support to verilog front-endClifford Wolf2017-10-071-0/+17
* Rename "write_verilog -nobasenradix" to "write_verilog -decimal"Clifford Wolf2017-10-031-16/+13
* Fixed wrong declaration in Verilog backenddh732017-10-011-3/+3
* Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ...dh732017-10-011-3/+16
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-4/+6
* Cleanups and fixed in write_verilog regarding reg initClifford Wolf2016-11-161-15/+61
* Added hex constant support to write_verilogClifford Wolf2016-11-031-4/+62