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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 19:14:07 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-01-02 13:12:17 +0000 |
| commit | efa278e232d20ea080743801bd91d55ec62955cf (patch) | |
| tree | 61971fdccdc1bb24169d78d0193eccc957232536 /backends/verilog | |
| parent | 4b9f619349e6b7452739631635ab3b5a4d94b522 (diff) | |
| download | yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.gz yosys-efa278e232d20ea080743801bd91d55ec62955cf.tar.bz2 yosys-efa278e232d20ea080743801bd91d55ec62955cf.zip | |
Fix typographical and grammatical errors and inconsistencies.
The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 71db25f98..2537e18e5 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1447,7 +1447,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } if (!module->processes.empty()) - log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n" + log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n" "can't always be mapped directly to Verilog always blocks. Unintended\n" "changes in simulation behavior are possible! Use \"proc\" to convert\n" "processes to logic networks and registers.\n", log_id(module)); |