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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 09:49:55 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-23 21:36:59 +0200 |
| commit | 846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2 (patch) | |
| tree | 8f736e6a2e208ed22d74c9f40cf9503dcd11c54c /backends/verilog | |
| parent | 0bf9d0087c43f9db3d56cb2bed17268def21eb67 (diff) | |
| download | yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.tar.gz yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.tar.bz2 yosys-846eb5ea98594daed7bf80a3e9c077a1ce7cf6f2.zip | |
Add $specify2/$specify3 support to write_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 1c65e79b7..6bb08fdb2 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1252,6 +1252,53 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) return true; } + if (cell->type.in("$specify2", "$specify3")) + { + f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); + + SigSpec en = cell->getPort("\\EN"); + if (en != State::S1) { + f << stringf("if ("); + dump_sigspec(f, cell->getPort("\\EN")); + f << stringf(") "); + } + + f << "("; + if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool()) + f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge "); + + dump_sigspec(f, cell->getPort("\\SRC")); + + f << " "; + if (cell->getParam("\\SRC_DST_PEN").as_bool()) + f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-"); + f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> "); + + if (cell->type == "$specify3") { + f << "("; + dump_sigspec(f, cell->getPort("\\DST")); + f << " "; + if (cell->getParam("\\DAT_DST_PEN").as_bool()) + f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-"); + f << ": "; + dump_sigspec(f, cell->getPort("\\DAT")); + f << ")"; + } else { + dump_sigspec(f, cell->getPort("\\DST")); + } + + f << stringf(") = (%d:%d:%d, %d:%d:%d);\n", + cell->getParam("\\T_RISE_MIN").as_int(), + cell->getParam("\\T_RISE_AVG").as_int(), + cell->getParam("\\T_RISE_MAX").as_int(), + cell->getParam("\\T_FALL_MIN").as_int(), + cell->getParam("\\T_FALL_AVG").as_int(), + cell->getParam("\\T_FALL_MAX").as_int()); + + f << stringf("%s" "endspecify\n", indent.c_str()); + return true; + } + // FIXME: $_SR_[PN][PN]_, $_DLATCH_[PN]_, $_DLATCHSR_[PN][PN][PN]_ // FIXME: $sr, $dlatch, $memrd, $memwr, $fsm |