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| author | dh73 <dh73_fpga@qq.com> | 2017-10-01 11:11:32 -0500 |
|---|---|---|
| committer | dh73 <dh73_fpga@qq.com> | 2017-10-01 11:11:32 -0500 |
| commit | e4808477531d31284244188637af3ccf89a21269 (patch) | |
| tree | b2e1edce67aae3e692a521efda0df394d1347cbd /backends/verilog | |
| parent | cbaba62401ca975bc9aee91b53e0b48fa59bd6c3 (diff) | |
| download | yosys-e4808477531d31284244188637af3ccf89a21269.tar.gz yosys-e4808477531d31284244188637af3ccf89a21269.tar.bz2 yosys-e4808477531d31284244188637af3ccf89a21269.zip | |
Fixed wrong declaration in Verilog backend
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 33f9a81e4..48e06dc7c 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -175,7 +175,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o if (set_signed && val < 0) f << stringf("-32'sd%u", -val); else { - if(!nobasenradix) + if(nobasenradix) f << stringf("%u", val); // There's no signed parameter on megawizard IP else f << stringf("32'%sd%u", set_signed ? "s" : "", val); @@ -1585,8 +1585,8 @@ struct VerilogBackend : public Backend { continue; } if (arg == "-nobasenradix") { - defparam = true; - continue; + nobasenradix = true; + continue; } if (arg == "-blackboxes") { blackboxes = true; |