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| author | Clifford Wolf <clifford@clifford.at> | 2019-05-07 19:55:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-05-07 19:55:36 +0200 |
| commit | 33738c174560c718723b6c860af002d1a8a91cea (patch) | |
| tree | 64a046776ac2259c1ad515b34d3a6f43d02da1c6 /backends/verilog | |
| parent | 0ee1759f00610b45f444a1248bf597b4c549ffa9 (diff) | |
| download | yosys-33738c174560c718723b6c860af002d1a8a91cea.tar.gz yosys-33738c174560c718723b6c860af002d1a8a91cea.tar.bz2 yosys-33738c174560c718723b6c860af002d1a8a91cea.zip | |
Fix handling of partial init attributes in write_verilog, fixes #997
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 9fd4ccbc8..827af5d85 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1618,7 +1618,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) SigSpec sig = active_sigmap(wire); Const val = wire->attributes.at("\\init"); for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++) - active_initdata[sig[i]] = val.bits.at(i); + if (val[i] == State::S0 || val[i] == State::S1) + active_initdata[sig[i]] = val[i]; } if (!module->processes.empty()) |