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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-11 07:25:52 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-11 07:25:52 +0200 |
| commit | 9112850800a92ed0e330d8470e1273116d78ba14 (patch) | |
| tree | c09bc1be5d109b3270f217614b21f9ef3ca3490d /backends/verilog | |
| parent | fd3d5cefad89a396c9807bf3b8dc7349c1a765f1 (diff) | |
| parent | 6a29e1f5b7e8ac36fcf8c5f00c509ebeaa5257e5 (diff) | |
| download | yosys-9112850800a92ed0e330d8470e1273116d78ba14.tar.gz yosys-9112850800a92ed0e330d8470e1273116d78ba14.tar.bz2 yosys-9112850800a92ed0e330d8470e1273116d78ba14.zip | |
Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark
write_verilog: write RTLIL::Sa aka - as Verilog ?
Diffstat (limited to 'backends/verilog')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 087c6fec6..a020d82b6 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -222,7 +222,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o case RTLIL::S1: bin_digits.push_back('1'); break; case RTLIL::Sx: bin_digits.push_back('x'); break; case RTLIL::Sz: bin_digits.push_back('z'); break; - case RTLIL::Sa: bin_digits.push_back('z'); break; + case RTLIL::Sa: bin_digits.push_back('?'); break; case RTLIL::Sm: log_error("Found marker state in final netlist."); } } @@ -251,6 +251,12 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o hex_digits.push_back('z'); continue; } + if (bit_3 == '?' || bit_2 == '?' || bit_1 == '?' || bit_0 == '?') { + if (bit_3 != '?' || bit_2 != '?' || bit_1 != '?' || bit_0 != '?') + goto dump_bin; + hex_digits.push_back('?'); + continue; + } int val = 8*(bit_3 - '0') + 4*(bit_2 - '0') + 2*(bit_1 - '0') + (bit_0 - '0'); hex_digits.push_back(val < 10 ? '0' + val : 'a' + val - 10); } @@ -270,7 +276,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o case RTLIL::S1: f << stringf("1"); break; case RTLIL::Sx: f << stringf("x"); break; case RTLIL::Sz: f << stringf("z"); break; - case RTLIL::Sa: f << stringf("z"); break; + case RTLIL::Sa: f << stringf("?"); break; case RTLIL::Sm: log_error("Found marker state in final netlist."); } } |