| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Make liberal use of IdString.in() | Eddie Hung | 2019-08-06 | 1 | -1/+1 |
| * | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+14 |
| * | Merge pull request #1203 from whitequark/write_verilog-zero-width-values | Clifford Wolf | 2019-07-18 | 1 | -1/+2 |
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| | * | write_verilog: dump zero width constants correctly. | whitequark | 2019-07-16 | 1 | -1/+2 |
| * | | Remove old $pmux_safe code from write_verilog | Clifford Wolf | 2019-07-17 | 1 | -5/+4 |
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| * | Merge pull request #1172 from whitequark/write_verilog-Sa-as-qmark | Clifford Wolf | 2019-07-11 | 1 | -2/+8 |
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| | * | write_verilog: write RTLIL::Sa aka - as Verilog ?. | whitequark | 2019-07-09 | 1 | -2/+8 |
| * | | write_verilog: fix placement of case attributes. NFC. | whitequark | 2019-07-09 | 1 | -3/+2 |
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| * | verilog_backend: dump attributes on SwitchRule. | whitequark | 2019-07-08 | 1 | -0/+1 |
| * | verilog_backend: dump attributes on CaseRule, as comments. | whitequark | 2019-07-08 | 1 | -6/+10 |
| * | Fix handling of partial init attributes in write_verilog, fixes #997 | Clifford Wolf | 2019-05-07 | 1 | -1/+2 |
| * | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -15/+71 |
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| * | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 |
| * | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 |
| * | Add support for zero-width signals to Verilog back-end, fixes #948 | Clifford Wolf | 2019-04-22 | 1 | -0/+8 |
| * | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -1/+1 |
| * | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -0/+4 |
| * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -2/+11 |
| * | Instead of INIT param on cells, use initial statement with hier ref as | Eddie Hung | 2019-02-17 | 1 | -18/+13 |
| * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 1 | -38/+41 |
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| | * | write_verilog: correctly emit asynchronous transparent ports. | whitequark | 2019-01-29 | 1 | -38/+41 |
| * | | Remove check for cell->name[0] == '$' | Eddie Hung | 2019-02-06 | 1 | -1/+1 |
| * | | Refactor | Eddie Hung | 2019-02-06 | 1 | -21/+5 |
| * | | write_verilog to cope with init attr on q when -noexpr | Eddie Hung | 2019-02-06 | 1 | -2/+32 |
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| * | Merge pull request #800 from whitequark/write_verilog_tribuf | Clifford Wolf | 2019-01-27 | 1 | -0/+12 |
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| | * | write_verilog: write $tribuf cell as ternary. | whitequark | 2019-01-27 | 1 | -0/+12 |
| * | | write_verilog: escape names that match SystemVerilog keywords. | whitequark | 2019-01-27 | 1 | -0/+27 |
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| * | Fix handling of $shiftx in Verilog back-end | Clifford Wolf | 2019-01-15 | 1 | -3/+6 |
| * | Fix typographical and grammatical errors and inconsistencies. | whitequark | 2019-01-02 | 1 | -1/+1 |
| * | write_verilog: handle the $shift cell. | whitequark | 2018-12-16 | 1 | -0/+29 |
| * | Merge pull request #736 from whitequark/select_assert_list | Clifford Wolf | 2018-12-16 | 1 | -1/+1 |
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| | * | write_verilog: add a missing newline. | whitequark | 2018-12-16 | 1 | -1/+1 |
| * | | write_verilog: correctly map RTLIL `sync init`. | whitequark | 2018-12-07 | 1 | -0/+2 |
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| * | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -1/+1 |
| * | adding offset info to memories | rafaeltp | 2018-10-18 | 1 | -2/+3 |
| * | Fixed typo in "verilog_write" help message | acw1251 | 2018-09-18 | 1 | -3/+3 |
| * | Add $lut support to Verilog back-end | Clifford Wolf | 2018-09-06 | 1 | -0/+13 |
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| * | Add $dlatch support to write_verilog | Clifford Wolf | 2018-04-22 | 1 | -0/+38 |
| * | Add $shiftx support to verilog front-end | Clifford Wolf | 2017-10-07 | 1 | -0/+17 |
| * | Rename "write_verilog -nobasenradix" to "write_verilog -decimal" | Clifford Wolf | 2017-10-03 | 1 | -16/+13 |
| * | Fixed wrong declaration in Verilog backend | dh73 | 2017-10-01 | 1 | -3/+3 |
| * | Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ... | dh73 | 2017-10-01 | 1 | -3/+16 |
| * | Add $_ANDNOT_ and $_ORNOT_ gates | Clifford Wolf | 2017-05-17 | 1 | -4/+6 |
| * | Cleanups and fixed in write_verilog regarding reg init | Clifford Wolf | 2016-11-16 | 1 | -15/+61 |
| * | Added hex constant support to write_verilog | Clifford Wolf | 2016-11-03 | 1 | -4/+62 |
| * | Adde "write_verilog -renameprefix -v" | Clifford Wolf | 2016-11-01 | 1 | -5/+23 |
| * | Bugfix in partial mem write handling in verilog back-end | Clifford Wolf | 2016-08-20 | 1 | -42/+26 |
| * | Added missing support for mem read enable ports to verilog back-end | Clifford Wolf | 2016-08-18 | 1 | -6/+14 |
