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Age
Files
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*
Removed yosys-svgviewer
Clifford Wolf
2014-09-02
1
-19
/
+18
*
Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
1
-1
/
+1
*
Added DPI-C documentation to README file
Clifford Wolf
2014-08-22
1
-0
/
+12
*
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf
2014-08-22
1
-2
/
+2
*
Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
1
-0
/
+27
*
Added support for non-standard """ macro bodies
Clifford Wolf
2014-08-13
1
-0
/
+9
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
1
-1
/
+0
*
Added support for non-standard "module mod_name(...);" syntax
Clifford Wolf
2014-08-04
1
-0
/
+5
*
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
1
-2
/
+1
*
Added links to some liberty files to README
Clifford Wolf
2014-06-28
1
-0
/
+8
*
Added more calls to "hierarchy" to README file
Clifford Wolf
2014-06-15
1
-3
/
+8
*
Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
1
-3
/
+13
*
Updated README
Clifford Wolf
2014-04-18
1
-18
/
+11
*
Added libs/minisat (copy of minisat git master)
Clifford Wolf
2014-03-12
1
-15
/
+0
*
Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
1
-1
/
+1
*
Updated todo items in README file
Clifford Wolf
2014-02-05
1
-2
/
+2
*
Added constant size expression support of sized constants
Clifford Wolf
2014-02-01
1
-0
/
+4
*
Added note about SystemVerilog assert statement to README
Clifford Wolf
2014-02-01
1
-0
/
+5
*
Tiny change in example script in README
Clifford Wolf
2014-01-29
1
-1
/
+1
*
Fixes and other changes in README
Clifford Wolf
2013-12-08
1
-7
/
+6
*
Tighter integration of ABC build
Clifford Wolf
2013-11-27
1
-4
/
+2
*
Updated TODOs
Clifford Wolf
2013-11-24
1
-2
/
+1
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
1
-0
/
+5
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
1
-2
/
+2
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
1
-2
/
+1
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
1
-3
/
+0
*
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
1
-1
/
+0
*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
1
-1
/
+0
*
Updated TODOs in README file
Clifford Wolf
2013-11-20
1
-6
/
+26
*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
1
-0
/
+4
*
Removed done or obsolete TODO items
Clifford Wolf
2013-11-07
1
-8
/
+0
*
Added support for "keep" attributes on wires
Clifford Wolf
2013-11-05
1
-3
/
+3
*
Added roadmap to readme file
Clifford Wolf
2013-11-02
1
-0
/
+9
*
Added paragraph to README file to avoid mycells.lib confusion
Clifford Wolf
2013-10-31
1
-0
/
+3
*
README file typo fix
Clifford Wolf
2013-10-31
1
-1
/
+1
*
Some additions to the README file
Clifford Wolf
2013-10-31
1
-0
/
+19
*
Added iopadmap pass
Clifford Wolf
2013-10-16
1
-1
/
+6
*
Added recommended apt-get commands to README
Clifford Wolf
2013-10-11
1
-2
/
+20
*
Updated TODO section in README
Clifford Wolf
2013-08-01
1
-9
/
+1
*
Added web site link to README
Clifford Wolf
2013-07-21
1
-0
/
+8
*
Added ast frontend refactoring to TODO
Clifford Wolf
2013-07-11
1
-0
/
+1
*
Documentation updates
Clifford Wolf
2013-07-04
1
-5
/
+2
*
Added "make abc" and "make install-abc"
Clifford Wolf
2013-06-08
1
-0
/
+5
*
Fixed README for new show command behavior (svg vs. ps)
Clifford Wolf
2013-04-27
1
-2
/
+6
*
Implemented TCL support (only via -c option at the moment)
Clifford Wolf
2013-03-28
1
-2
/
+2
*
Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
1
-0
/
+6
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
1
-0
/
+6
*
Reorganized TODOs
Clifford Wolf
2013-03-24
1
-24
/
+13
*
Added mem2reg option to verilog frontend
Clifford Wolf
2013-03-24
1
-0
/
+3
*
added a TODO
Johann Glaser
2013-03-18
1
-0
/
+2
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