| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Enable async load dff emit by default in Verific | Miodrag Milanovic | 2021-10-27 | 1 | -1/+1 |
| * | Revert "Compile option for enabling async load verific support" | Miodrag Milanovic | 2021-10-27 | 2 | -8/+1 |
| * | proc_dff: Emit $aldff. | Marcelina Kościelnicka | 2021-10-27 | 1 | -32/+7 |
| * | dfflegalize: Add tests for aldff lowering. | Marcelina Kościelnicka | 2021-10-27 | 2 | -0/+240 |
| * | dfflegalize: Add tests targetting aldff. | Marcelina Kościelnicka | 2021-10-27 | 7 | -7/+320 |
| * | dfflegalize: Refactor, add aldff support. | Marcelina Kościelnicka | 2021-10-27 | 12 | -1053/+1137 |
| * | Bump version | github-actions[bot] | 2021-10-27 | 1 | -1/+1 |
| * | verilog: use derived module info to elaborate cell connections | Zachary Snow | 2021-10-25 | 15 | -42/+397 |
| * | Split out logic for reprocessing an AstModule | Rupert Swarbrick | 2021-10-25 | 5 | -28/+61 |
| * | Bump version | github-actions[bot] | 2021-10-26 | 1 | -1/+1 |
| * | Compile option for enabling async load verific support | Miodrag Milanovic | 2021-10-25 | 2 | -1/+8 |
| * | Bump version | github-actions[bot] | 2021-10-22 | 1 | -1/+1 |
| * | Change implicit conversions from bool to Sig* to explicit. | Marcelina Kościelnicka | 2021-10-21 | 2 | -6/+8 |
| * | Merge pull request #3057 from YosysHQ/claire/verific_latches | Claire Xen | 2021-10-21 | 1 | -4/+61 |
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| | * | Fix verific.cc PRIM_DLATCH handling | Claire Xenia Wolf | 2021-10-21 | 1 | -1/+7 |
| | * | Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS} | Claire Xenia Wolf | 2021-10-21 | 1 | -4/+55 |
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| * | extract_reduce: Refactor and fix input signal construction. | Marcelina Kościelnicka | 2021-10-21 | 2 | -63/+46 |
| * | Bump version | github-actions[bot] | 2021-10-21 | 1 | -1/+1 |
| * | If verific have vhdl lib it is required by other libs | Miodrag Milanovic | 2021-10-20 | 1 | -0/+4 |
| * | Forgot to remove from main list | Miodrag Milanovic | 2021-10-20 | 1 | -1/+1 |
| * | Option to disable verific VHDL support | Miodrag Milanovic | 2021-10-20 | 3 | -11/+50 |
| * | Bump version | github-actions[bot] | 2021-10-20 | 1 | -1/+1 |
| * | Fixed Verific parser error in ice40 cell library | Claire Xenia Wolf | 2021-10-19 | 1 | -22/+62 |
| * | Merge pull request #3045 from galibert/master | Miodrag Milanović | 2021-10-19 | 1 | -0/+18 |
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| | * | CycloneV: Add (passthrough) support for cyclonev_oscillator | Olivier Galibert | 2021-10-17 | 1 | -1/+11 |
| | * | CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_pu... | Olivier Galibert | 2021-10-17 | 1 | -0/+8 |
| * | | Fixes in vcdcd.pl for newer Perl versions | Claire Xenia Wolf | 2021-10-19 | 1 | -3/+3 |
| * | | Bump version | github-actions[bot] | 2021-10-18 | 1 | -1/+1 |
| * | | dfflegalize: remove redundant check for initialized dlatch | Paul Annesley | 2021-10-17 | 1 | -4/+0 |
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| * | Bump version | github-actions[bot] | 2021-10-16 | 1 | -1/+1 |
| * | Merge pull request #3044 from YosysHQ/micko/verific_bufif1 | Claire Xen | 2021-10-15 | 1 | -2/+2 |
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| | * | Support PRIM_BUFIF1 primitive | Miodrag Milanovic | 2021-10-14 | 1 | -2/+2 |
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| * | Bump version | github-actions[bot] | 2021-10-12 | 1 | -1/+1 |
| * | Merge pull request #3039 from YosysHQ/claire/verific_aldff | Claire Xen | 2021-10-11 | 2 | -1/+91 |
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| | * | Add Verific adffe/dffsre/aldffe FIXMEs | Claire Xenia Wolf | 2021-10-11 | 1 | -0/+3 |
| | * | Fixes and add comments for open FIXME items | Claire Xenia Wolf | 2021-10-08 | 1 | -1/+34 |
| | * | Add support for $aldff flip-flops to verific importer | Claire Xenia Wolf | 2021-10-08 | 2 | -1/+55 |
| * | | Merge pull request #3040 from YosysHQ/micko/split_module_ports | Claire Xen | 2021-10-11 | 1 | -0/+2 |
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| | * | | Split module ports, 20 per line | Miodrag Milanovic | 2021-10-09 | 1 | -0/+2 |
| * | | | Merge pull request #3041 from YosysHQ/mmicko/module_attr | Claire Xen | 2021-10-11 | 1 | -0/+1 |
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| | * | | Import module attributes from Verific | Miodrag Milanovic | 2021-10-10 | 1 | -0/+1 |
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| * | | Bump version | github-actions[bot] | 2021-10-09 | 1 | -1/+1 |
| * | | Fix a regression from #3035. | Marcelina Kościelnicka | 2021-10-08 | 2 | -1/+22 |
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| * | Bump version | github-actions[bot] | 2021-10-08 | 1 | -1/+1 |
| * | FfData: some refactoring. | Marcelina Kościelnicka | 2021-10-07 | 14 | -546/+660 |
| * | Bump version | github-actions[bot] | 2021-10-05 | 1 | -1/+1 |
| * | verific set db_infer_set_reset_registers | Miodrag Milanovic | 2021-10-04 | 1 | -0/+1 |
| * | Bump version | github-actions[bot] | 2021-10-03 | 1 | -1/+1 |
| * | Hook up $aldff support in various passes. | Marcelina Kościelnicka | 2021-10-02 | 9 | -11/+77 |
| * | zinit: Refactor to use FfData. | Marcelina Kościelnicka | 2021-10-02 | 1 | -101/+38 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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