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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-2515-42/+397
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-255-28/+61
* Bump versiongithub-actions[bot]2021-10-261-1/+1
* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-252-1/+8
* Bump versiongithub-actions[bot]2021-10-221-1/+1
* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-212-6/+8
* Merge pull request #3057 from YosysHQ/claire/verific_latchesClaire Xen2021-10-211-4/+61
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| * Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| * Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
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* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-212-63/+46
* Bump versiongithub-actions[bot]2021-10-211-1/+1
* If verific have vhdl lib it is required by other libsMiodrag Milanovic2021-10-201-0/+4
* Forgot to remove from main listMiodrag Milanovic2021-10-201-1/+1
* Option to disable verific VHDL supportMiodrag Milanovic2021-10-203-11/+50
* Bump versiongithub-actions[bot]2021-10-201-1/+1
* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
* Merge pull request #3045 from galibert/masterMiodrag Milanović2021-10-191-0/+18
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| * CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
| * CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_pu...Olivier Galibert2021-10-171-0/+8
* | Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
* | Bump versiongithub-actions[bot]2021-10-181-1/+1
* | dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
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* Bump versiongithub-actions[bot]2021-10-161-1/+1
* Merge pull request #3044 from YosysHQ/micko/verific_bufif1Claire Xen2021-10-151-2/+2
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| * Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Bump versiongithub-actions[bot]2021-10-121-1/+1
* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
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| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
* | Merge pull request #3040 from YosysHQ/micko/split_module_portsClaire Xen2021-10-111-0/+2
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| * | Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
* | | Merge pull request #3041 from YosysHQ/mmicko/module_attrClaire Xen2021-10-111-0/+1
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| * | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* | Bump versiongithub-actions[bot]2021-10-091-1/+1
* | Fix a regression from #3035.Marcelina Kościelnicka2021-10-082-1/+22
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* Bump versiongithub-actions[bot]2021-10-081-1/+1
* FfData: some refactoring.Marcelina Kościelnicka2021-10-0714-546/+660
* Bump versiongithub-actions[bot]2021-10-051-1/+1
* verific set db_infer_set_reset_registersMiodrag Milanovic2021-10-041-0/+1
* Bump versiongithub-actions[bot]2021-10-031-1/+1
* Hook up $aldff support in various passes.Marcelina Kościelnicka2021-10-029-11/+77
* zinit: Refactor to use FfData.Marcelina Kościelnicka2021-10-021-101/+38
* kernel/ff: Refactor FfData to enable FFs with async load.Marcelina Kościelnicka2021-10-0210-325/+565
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-029-2/+527
* Specify minimum bison version 3.0+Zachary Snow2021-10-012-0/+4
* simplemap: refactor to use FfData.Marcelina Kościelnicka2021-10-023-290/+26
* Merge pull request #3017 from YosysHQ/claire/short_rtlil_x_constMiodrag Milanović2021-09-281-9/+13
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| * Add optimization to rtlil back-end for all-x parameter valuesClaire Xenia Wolf2021-09-271-9/+13
* | Bump versiongithub-actions[bot]2021-09-281-1/+1
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