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* Bump versiongithub-actions[bot]2021-10-301-1/+1
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* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
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* Update command reference part of manualMiodrag Milanovic2021-10-291-340/+1444
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* Bump versiongithub-actions[bot]2021-10-281-1/+1
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* Merge pull request #3063 from YosysHQ/micko/verific_aldffMiodrag Milanović2021-10-272-8/+1
|\ | | | | Enable async load dff emit by default in Verific
| * Enable async load dff emit by default in VerificMiodrag Milanovic2021-10-271-1/+1
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| * Revert "Compile option for enabling async load verific support"Miodrag Milanovic2021-10-272-8/+1
| | | | | | | | This reverts commit b8624ad2aef941776f5b4a08f66f8d43e70f8467.
* | ecp5: Add support for mapping aldff.Marcelina Kościelnicka2021-10-272-13/+13
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* proc_dff: Emit $aldff.Marcelina Kościelnicka2021-10-271-32/+7
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* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
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* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
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* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-2712-1053/+1137
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* Bump versiongithub-actions[bot]2021-10-271-1/+1
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-2515-42/+397
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Split out logic for reprocessing an AstModuleRupert Swarbrick2021-10-255-28/+61
| | | | | This will enable other features to use same core logic for replacing an existing AstModule with a newly elaborated version.
* Bump versiongithub-actions[bot]2021-10-261-1/+1
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* Compile option for enabling async load verific supportMiodrag Milanovic2021-10-252-1/+8
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* Bump versiongithub-actions[bot]2021-10-221-1/+1
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* Change implicit conversions from bool to Sig* to explicit.Marcelina Kościelnicka2021-10-212-6/+8
| | | | Also fixes some completely broken code in extract_reduce.
* Merge pull request #3057 from YosysHQ/claire/verific_latchesClaire Xen2021-10-211-4/+61
|\ | | | | Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}
| * Fix verific.cc PRIM_DLATCH handlingClaire Xenia Wolf2021-10-211-1/+7
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Initial Verific impoter support for {PRIM,WIDE_OPER}_DLATCH{,RS}Claire Xenia Wolf2021-10-211-4/+55
|/ | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-212-63/+46
| | | | Fixes #3047.
* Bump versiongithub-actions[bot]2021-10-211-1/+1
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* If verific have vhdl lib it is required by other libsMiodrag Milanovic2021-10-201-0/+4
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* Forgot to remove from main listMiodrag Milanovic2021-10-201-1/+1
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* Option to disable verific VHDL supportMiodrag Milanovic2021-10-203-11/+50
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* Bump versiongithub-actions[bot]2021-10-201-1/+1
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* Fixed Verific parser error in ice40 cell libraryClaire Xenia Wolf2021-10-191-22/+62
| | | | non-net output port 'Q' cannot be initialized at declaration in SystemVerilog mode
* Merge pull request #3045 from galibert/masterMiodrag Milanović2021-10-191-0/+18
|\ | | | | CycloneV: Add (passthrough) support for cyclonev_hps_interface_mpu_general_purpose
| * CycloneV: Add (passthrough) support for cyclonev_oscillatorOlivier Galibert2021-10-171-1/+11
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| * CycloneV: Add (passthrough) support for ↵Olivier Galibert2021-10-171-0/+8
| | | | | | | | cyclonev_hps_interface_mpu_general_purpose
* | Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Bump versiongithub-actions[bot]2021-10-181-1/+1
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* | dfflegalize: remove redundant check for initialized dlatchPaul Annesley2021-10-171-4/+0
|/ | | | | | This if condition is repeated verbatim, and I can't imagine a legitimate way the inputs could change in between. I imagine it's a copy/paste mistake.
* Bump versiongithub-actions[bot]2021-10-161-1/+1
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* Merge pull request #3044 from YosysHQ/micko/verific_bufif1Claire Xen2021-10-151-2/+2
|\ | | | | Support PRIM_BUFIF1 primitive, fixes #2981
| * Support PRIM_BUFIF1 primitiveMiodrag Milanovic2021-10-141-2/+2
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* Bump versiongithub-actions[bot]2021-10-121-1/+1
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* Merge pull request #3039 from YosysHQ/claire/verific_aldffClaire Xen2021-10-112-1/+91
|\ | | | | Add support for $aldff flip-flops to verific importer
| * Add Verific adffe/dffsre/aldffe FIXMEsClaire Xenia Wolf2021-10-111-0/+3
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Fixes and add comments for open FIXME itemsClaire Xenia Wolf2021-10-081-1/+34
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * Add support for $aldff flip-flops to verific importerClaire Xenia Wolf2021-10-082-1/+55
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | Merge pull request #3040 from YosysHQ/micko/split_module_portsClaire Xen2021-10-111-0/+2
|\ \ | | | | | | Split module ports, 20 per line
| * | Split module ports, 20 per lineMiodrag Milanovic2021-10-091-0/+2
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* | | Merge pull request #3041 from YosysHQ/mmicko/module_attrClaire Xen2021-10-111-0/+1
|\ \ \ | |/ / |/| | Import module attributes from Verific
| * | Import module attributes from VerificMiodrag Milanovic2021-10-101-0/+1
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* | Bump versiongithub-actions[bot]2021-10-091-1/+1
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* | Fix a regression from #3035.Marcelina Kościelnicka2021-10-082-1/+22
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* Bump versiongithub-actions[bot]2021-10-081-1/+1
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