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| * | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-227-44/+115
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| * | | | | | | | | | | | | | | Add '-nosrl' option to synth_xilinxEddie Hung2019-03-211-6/+16
| * | | | | | | | | | | | | | | OptEddie Hung2019-03-211-1/+1
| * | | | | | | | | | | | | | | Fix spacingEddie Hung2019-03-201-239/+239
| * | | | | | | | | | | | | | | Fine tune cells_map.vEddie Hung2019-03-201-19/+15
| * | | | | | | | | | | | | | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable lengthEddie Hung2019-03-192-58/+34
| * | | | | | | | | | | | | | | Add support for variable length Xilinx SRL > 128Eddie Hung2019-03-192-17/+67
| * | | | | | | | | | | | | | | Restore original synth_xilinx commandsEddie Hung2019-03-191-1/+2
| * | | | | | | | | | | | | | | Fix spacingEddie Hung2019-03-191-1/+1
| * | | | | | | | | | | | | | | shregmap -tech xilinx to delete $shiftx for var length SRLEddie Hung2019-03-191-10/+3
| * | | | | | | | | | | | | | | Fix INIT for variable length SRs that have been bumped up oneEddie Hung2019-03-191-1/+1
| * | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1953-38/+2398
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| * | | | | | | | | | | | | | | | Make output port a non chain userEddie Hung2019-03-191-2/+4
| * | | | | | | | | | | | | | | | Fix shregmap to correctly recognise non chain users; cleanupEddie Hung2019-03-181-17/+15
| * | | | | | | | | | | | | | | | shiftx NULL pointer checkEddie Hung2019-03-181-8/+10
| * | | | | | | | | | | | | | | | CleanupEddie Hung2019-03-161-35/+25
| * | | | | | | | | | | | | | | | Only accept <128 for variable length, only if $shiftx exclusiveEddie Hung2019-03-162-13/+18
| * | | | | | | | | | | | | | | | Cleanup synth_xilinxEddie Hung2019-03-152-3/+2
| * | | | | | | | | | | | | | | | WorkingEddie Hung2019-03-153-274/+434
| * | | | | | | | | | | | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted firstEddie Hung2019-03-141-16/+32
| * | | | | | | | | | | | | | | | MisspellEddie Hung2019-03-141-1/+1
| * | | | | | | | | | | | | | | | Revert "Add shregmap -init_msb_first and use in synth_xilinx"Eddie Hung2019-03-142-17/+4
| * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-03-1482-584/+2483
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| * | | | | | | | | | | | | | | | | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-142-4/+16
| * | | | | | | | | | | | | | | | | Fix cells_map for SRLEddie Hung2019-03-141-19/+17
| * | | | | | | | | | | | | | | | | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
| * | | | | | | | | | | | | | | | | Refactor $__SHREG__ in cells_map.vEddie Hung2019-03-131-32/+24
| * | | | | | | | | | | | | | | | | Remove SRL16/32 from cells_xtraEddie Hung2019-02-282-18/+2
| * | | | | | | | | | | | | | | | | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
| * | | | | | | | | | | | | | | | | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
| * | | | | | | | | | | | | | | | | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
| * | | | | | | | | | | | | | | | | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-282-22/+19
| * | | | | | | | | | | | | | | | | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
| * | | | | | | | | | | | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32Eddie Hung2019-02-281-0/+71
* | | | | | | | | | | | | | | | | | Merge pull request #952 from YosysHQ/clifford/fix370Clifford Wolf2019-04-221-3/+18
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| * | | | | | | | | | | | | | | | | | Determine correct signedness and expression width in for loop unrolling, fixe...Clifford Wolf2019-04-221-3/+18
* | | | | | | | | | | | | | | | | | | Merge pull request #951 from YosysHQ/clifford/logdebugClifford Wolf2019-04-2211-53/+183
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| * | | | | | | | | | | | | | | | | | | Add log_debug() frameworkClifford Wolf2019-04-2211-53/+183
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* | | | | | | | | | | | | | | | | | | Merge pull request #949 from YosysHQ/clifford/pmux2shimproveClifford Wolf2019-04-222-3/+24
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| * | | | | | | | | | | | | | | | | | | Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| * | | | | | | | | | | | | | | | | | | Add full_pmux feature to pmux2shiftxClifford Wolf2019-04-221-1/+22
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* | | | | | | | | | | | | | | | | | | Merge pull request #953 from YosysHQ/clifford/fix948Clifford Wolf2019-04-221-0/+8
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| * | | | | | | | | | | | | | | | | | Add support for zero-width signals to Verilog back-end, fixes #948Clifford Wolf2019-04-221-0/+8
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* | | | | | | | | | | | | | | | | | Merge pull request #950 from whitequark/attrmap_remove_wildcardClifford Wolf2019-04-221-1/+3
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| * | | | | | | | | | | | | | | | | attrmap: extend -remove to allow removing attributes with any value.whitequark2019-04-221-1/+3
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* | | | | | | | | | | | | | | | | Set ENABLE_LIBYOSYS=0 by defaultClifford Wolf2019-04-221-1/+1
* | | | | | | | | | | | | | | | | Set ENABLE_PYOSYS=0 by defaultClifford Wolf2019-04-221-1/+1
* | | | | | | | | | | | | | | | | Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-2215-10/+2472
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| * | | | | | | | | | | | | | | | | Suppress error from the compiler run during libboost-python* detectionBenedikt Tutzer2019-04-071-4/+4
| * | | | | | | | | | | | | | | | | Autodetect Python paths and boost python libraries for different distributionsBenedikt Tutzer2019-04-051-8/+24
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