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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-13 17:13:52 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-03-13 17:13:52 -0700 |
| commit | edca2f116373df7819ec68906ce74f15456168c2 (patch) | |
| tree | b2cacb274bedb2de8e57901438d25e9d636e5b61 | |
| parent | 24f129ddfb6496226801861a15e4e9518217dd76 (diff) | |
| download | yosys-edca2f116373df7819ec68906ce74f15456168c2.tar.gz yosys-edca2f116373df7819ec68906ce74f15456168c2.tar.bz2 yosys-edca2f116373df7819ec68906ce74f15456168c2.zip | |
Move shregmap until after first techmap
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 280c6b729..ce597ea4a 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -103,9 +103,9 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); - log(" shregmap -init\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); + log(" shregmap -init -params -enpol any_or_none\n"); log(" opt -fast\n"); log("\n"); log(" map_luts:\n"); @@ -223,9 +223,9 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -fast"); } |