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author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:00 -0800 |
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committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 13:56:00 -0800 |
commit | 8aab7fe7e64b1c213d924126e30994ab7b6d4625 (patch) | |
tree | fb1d094769e8a56d4babdb03550cb88d6f332405 | |
parent | fe4d6898de378260c659dca08398fa434d71f7f0 (diff) | |
download | yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.tar.gz yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.tar.bz2 yosys-8aab7fe7e64b1c213d924126e30994ab7b6d4625.zip |
Fix SRL16/32 techmap off-by-one
-rw-r--r-- | techlibs/xilinx/cells_map.v | 42 |
1 files changed, 24 insertions, 18 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 168cbfa04..d2cc96969 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -88,19 +88,22 @@ endmodule module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; parameter [DEPTH-1:0] INIT = 0; - parameter CLKPOL = 0; + parameter CLKPOL = 1; parameter ENPOL = 2; wire CE; generate - if (ENPOL != 0) + if (ENPOL == 0) + assign CE = ~E; + else if (ENPOL == 1) assign CE = E; else - assign CE = ~E; + assign CE = 1'b1; if (DEPTH == 1) begin FDRE #(.INIT(INIT), .IS_C_INVERTED(~CLKPOL[0]), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0)); end else if (DEPTH <= 16) begin - SRL16E #(.INIT(INIT), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(DEPTH[0]), .A1(DEPTH[1]), .A2(DEPTH[2]), .A3(DEPTH[3]), .CE(CE), .CLK(C), .D(D), .Q(Q)); + localparam [3:0] A = DEPTH - 1; + SRL16E #(.INIT(INIT), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CE(CE), .CLK(C), .D(D), .Q(Q)); end else if (DEPTH == 17) begin wire T0; @@ -108,7 +111,7 @@ module \$__SHREG_ (input C, input D, input E, output Q); \$__SHREG_ #(.DEPTH(1), .INIT(INIT[DEPTH-1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .E(E), .Q(Q)); end else if (DEPTH <= 32) begin - SRLC32E #(.INIT(INIT), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(DEPTH), .CE(CE), .CLK(C), .D(D), .Q(Q)); + SRLC32E #(.INIT(INIT), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(DEPTH-1), .CE(CE), .CLK(C), .D(D), .Q(Q)); end else if (DEPTH == 33 || DEPTH == 49) begin wire T0; @@ -117,9 +120,10 @@ module \$__SHREG_ (input C, input D, input E, output Q); end else if (DEPTH <= 64) begin wire T0, T1, T2; - SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(DEPTH), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + localparam [5:0] A = DEPTH-1; + SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); \$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-1:32]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .E(E), .Q(T2)); - MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(DEPTH[5])); + MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(A[5])); end else if (DEPTH == 65 || DEPTH == 81) begin wire T0; @@ -127,13 +131,14 @@ module \$__SHREG_ (input C, input D, input E, output Q); \$__SHREG_ #(.DEPTH(1), .INIT(INIT[DEPTH-1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .E(E), .Q(Q)); end else if (DEPTH <= 96) begin + localparam [6:0] A = DEPTH-1; wire T0, T1, T2, T3, T4, T5, T6; - SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(DEPTH[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); - SRLC32E #(.INIT(INIT[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(DEPTH[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); \$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-1:64]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .E(E), .Q(T4)); - MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(DEPTH[5])); - MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(DEPTH[5])); - MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(DEPTH[6])); + MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(A[5])); + MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(A[5])); + MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(A[6])); end else if (DEPTH == 97 || DEPTH == 113) begin wire T0; @@ -141,14 +146,15 @@ module \$__SHREG_ (input C, input D, input E, output Q); \$__SHREG_ #(.DEPTH(1), .INIT(INIT[DEPTH-1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .E(E), .Q(Q)); end else if (DEPTH <= 128) begin + localparam [6:0] A = DEPTH-1; wire T0, T1, T2, T3, T4, T5, T6, T7, T8; - SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(DEPTH[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); - SRLC32E #(.INIT(INIT[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(DEPTH[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); - SRLC32E #(.INIT(INIT[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(DEPTH[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); + SRLC32E #(.INIT(INIT[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1)); + SRLC32E #(.INIT(INIT[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3)); + SRLC32E #(.INIT(INIT[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5)); \$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-1:96]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .E(E), .Q(T6)); - MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(DEPTH[5])); - MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(DEPTH[5])); - MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(DEPTH[6])); + MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(A[5])); + MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(A[5])); + MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(A[6])); end else begin wire T0, T1; |