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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 20:01:09 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-04-22 20:01:09 +0200 |
| commit | 3be5aac52c8703aa00ff591fd184da1ac39df678 (patch) | |
| tree | 1b9a402b5151ffb19b85287b4989489ce5c7a77d | |
| parent | 9050b5e1915b05f55c1db279566f34202905f02a (diff) | |
| parent | 0e0c80fac883a6f512a94aecdc3c915b8cacb562 (diff) | |
| download | yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.tar.gz yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.tar.bz2 yosys-3be5aac52c8703aa00ff591fd184da1ac39df678.zip | |
Merge pull request #953 from YosysHQ/clifford/fix948
Add support for zero-width signals to Verilog back-end
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 855409d0b..9967482d6 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -187,6 +187,10 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o { if (width < 0) width = data.bits.size() - offset; + if (width == 0) { + f << "\"\""; + return; + } if (nostr) goto dump_hex; if ((data.flags & RTLIL::CONST_FLAG_STRING) == 0 || width != (int)data.bits.size()) { @@ -340,6 +344,10 @@ void dump_sigchunk(std::ostream &f, const RTLIL::SigChunk &chunk, bool no_decima void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) { + if (GetSize(sig) == 0) { + f << "\"\""; + return; + } if (sig.is_chunk()) { dump_sigchunk(f, sig.as_chunk()); } else { |