iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Add SB_LUT4 to box library	Eddie Hung	2019-04-16	3	-0/+16
*	Add ice40 box files	Eddie Hung	2019-04-16	6	-1/+27
*	abc9 to output some more info	Eddie Hung	2019-04-16	1	-1/+2
*	CIs before PIs; also sort each cell's connections before iterating	Eddie Hung	2019-04-16	1	-5/+7
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-16	1	-28/+0
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\| *	Merge pull request #939 from YosysHQ/revert895	Eddie Hung	2019-04-16	1	-28/+0
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\| \| *	Revert #895	Eddie Hung	2019-04-16	1	-28/+0
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* \|	Port from xc7mux branch	Eddie Hung	2019-04-16	3	-54/+167
* \|	Re-enable partsel.v test	Eddie Hung	2019-04-16	1	-1/+0
* \|	abc9 to call "setundef -zero" behaving as for abc	Eddie Hung	2019-04-16	1	-0/+3
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-15	3	-6/+5
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\| *	Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch	Eddie Hung	2019-04-15	2	-4/+3
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\| \| *	Revert "Recognise default entry in case even if all cases covered (fix for #9...	Eddie Hung	2019-04-15	2	-4/+3
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\| *	Merge pull request #936 from YosysHQ/README-fix-quotes	Eddie Hung	2019-04-15	1	-2/+2
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\| \| *	README: fix some incorrect quoting.	whitequark	2019-04-15	1	-2/+2
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* \|	Forgot backslashes	Eddie Hung	2019-04-12	1	-1/+1
* \|	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	Eddie Hung	2019-04-12	2	-18/+8
* \|	abc to ignore __dummy_o__ and __const[01]__ when re-integrating	Eddie Hung	2019-04-12	1	-6/+20
* \|	Output __const0__ and __const1__ CIs	Eddie Hung	2019-04-12	1	-7/+10
* \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-04-12	1	-12/+32
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\| * \|	Fix inout handling for -map option	Eddie Hung	2019-04-12	1	-10/+30
* \| \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-04-12	0	-0/+0
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\| * \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-12	7	-50/+76
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* \| \|	Use -map instead of -symbols for aiger	Eddie Hung	2019-04-12	1	-2/+3
* \| \|	ci_bits and co_bits now a list, order is important for ABC	Eddie Hung	2019-04-12	1	-24/+34
* \| \|	Also cope with duplicated CIs	Eddie Hung	2019-04-12	1	-5/+23
* \| \|	WIP	Eddie Hung	2019-04-12	1	-14/+68
* \| \|	Comment out	Eddie Hung	2019-04-12	1	-1/+1
* \| \|	Add support for synth_xilinx -abc9 and ignore abc9 -dress opt	Eddie Hung	2019-04-12	2	-1/+14
* \| \|	Cope with an output having same name as an input (i.e. CO)	Eddie Hung	2019-04-12	1	-5/+23
* \| \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-12	7	-50/+76
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\| *	Merge pull request #928 from litghost/add_xc7_sim_models	Eddie Hung	2019-04-12	3	-41/+60
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\| \| *	Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.	Keith Rothman	2019-04-12	3	-52/+14
\| \| *	Fix LUT6_2 definition.	Keith Rothman	2019-04-09	1	-3/+3
\| \| *	Add additional cells sim models for core 7-series primatives.	Keith Rothman	2019-04-09	1	-0/+57
\| * \|	Merge pull request #933 from dh73/master	Clifford Wolf	2019-04-12	1	-3/+9
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\| \| * \|	Fixing issues in CycloneV cell sim	Diego	2019-04-11	1	-3/+9
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\| * \|	Merge pull request #932 from YosysHQ/eddie/fixdlatch	Clifford Wolf	2019-04-12	2	-3/+4
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\| \| *	Add default entry to testcase	Eddie Hung	2019-04-11	1	-2/+3
\| \| *	Recognise default entry in case even if all cases covered (#931)	Eddie Hung	2019-04-11	1	-1/+1
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\| *	Fix a few typos	Eddie Hung	2019-04-08	1	-3/+3
* \|	Add non-input bits driven by unrecognised cells as ci_bits	Eddie Hung	2019-04-10	1	-1/+1
* \|	parse_aiger() to rename all $lut cells after "clean"	Eddie Hung	2019-04-10	1	-24/+21
* \|	More space fixing	Eddie Hung	2019-04-08	1	-2/+2
* \|	Fix spacing	Eddie Hung	2019-04-08	1	-29/+29
* \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	115	-710/+5842
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\| *	Merge pull request #919 from YosysHQ/multiport_transp	Clifford Wolf	2019-04-08	1	-1/+2
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\| \| *	memory_bram: Fix multiport make_transp	David Shah	2019-04-07	1	-1/+2
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\| *	Add "read_ilang -lib"	Clifford Wolf	2019-04-05	5	-3/+39
\| *	Added missing argument checking to "mutate" command	Clifford Wolf	2019-04-04	1	-0/+32