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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 16:39:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 16:39:16 -0700 |
| commit | ae2653c50f196a0480e715c609852218f7c57090 (patch) | |
| tree | c3ec54740549f3a5cdca640b22aeca3290ffd3a3 | |
| parent | e7a8955818b8b0fee02673607b429f1de0f7164e (diff) | |
| download | yosys-ae2653c50f196a0480e715c609852218f7c57090.tar.gz yosys-ae2653c50f196a0480e715c609852218f7c57090.tar.bz2 yosys-ae2653c50f196a0480e715c609852218f7c57090.zip | |
abc9 to output some more info
| -rw-r--r-- | passes/techmap/abc9.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index b14eef485..e28e3e59a 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -343,7 +343,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri else abc_script += stringf("read_library %s/stdcells.genlib; ", tempdir_name.c_str()); - abc_script += stringf("&read %s/input.xaig; &ps ", tempdir_name.c_str()); + abc_script += stringf("&read %s/input.xaig; &ps; ", tempdir_name.c_str()); if (!script_file.empty()) { if (script_file[0] == '+') { @@ -388,6 +388,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3); abc_script += stringf("; &write %s/output.aig", tempdir_name.c_str()); + abc_script += "; &ps -l -s"; abc_script = add_echos_to_abc_cmd(abc_script); for (size_t i = 0; i+1 < abc_script.size(); i++) |